Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6060387 | Transistor fabrication process in which a contact metallization is formed with different silicide thickness over gate interconnect material and transistor source/drain regions | Adam Shepela, Bjorn K. A. Zetterlund | 2000-05-09 |
| 5296392 | Method of forming trench isolated regions with sidewall doping | Walter Metz | 1994-03-22 |
| 5175122 | Planarization process for trench isolation in integrated circuit manufacture | Ching-Tai Wang | 1992-12-29 |
| 5077234 | Planarization process utilizing three resist layers | John P. Scoopo, Frances P. Alvarez | 1991-12-31 |