Issued Patents All Time
Showing 1–25 of 235 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11867759 | Synchronizing a device that has been power cycled to an already operational system | — | 2024-01-09 |
| 11580264 | Systems and methods for controlling access to secure debugging and profiling features of a computer system | — | 2023-02-14 |
| 11567129 | Synchronizing a device that has been power cycled to an already operational system | — | 2023-01-31 |
| 10955471 | Operating state machine controllers after powering, decoupling, monitoring, coupling communications | — | 2021-03-23 |
| 10649029 | TCKC/TMSC counter, gating circuitry for selection, deselection, technology specific outputs | — | 2020-05-12 |
| RE47864 | Series equivalent scans across multiple scan topologies | — | 2020-02-18 |
| 10539594 | Detecting power supply sag in an integrated circuit | — | 2020-01-21 |
| 10438023 | Pipeline processor data and attribute register, secure emulation logic, gating | — | 2019-10-08 |
| 10371748 | Monitoring communication link in powered-up device for synchronization point sequence | — | 2019-08-06 |
| 10101391 | Adapter circuitry with link and system interfaces to core circuitry | — | 2018-10-16 |
| 10060956 | Detecting power supply sag in an integrated circuit | — | 2018-08-28 |
| 10054638 | TCK, TMS(C) clock, gating circuitry providing selection and deselection outputs | — | 2018-08-21 |
| 10048314 | Scan path only one-bit scan register when component not selected | Robert A. McGowan | 2018-08-14 |
| 10025955 | Pipeline processor execution stages, secure emulation logic, gating debug/profile output | — | 2018-07-17 |
| 9977079 | Operating two tap system after detecting shared bus synchronization sequence | — | 2018-05-22 |
| 9952285 | Adapter circuitry with global bypass register, legacy test data, multiplexer | — | 2018-04-24 |
| 9933484 | Taps with TO-T2, T4 classes with, without topology selection logic | — | 2018-04-03 |
| 9903914 | Target system recognizing synchronization point sequence on mode select input | — | 2018-02-27 |
| 9903912 | Status register between test data I/O of scan port SUT | Robert A. McGowan | 2018-02-27 |
| 9784792 | Taps of different scan classes with, without topology selection logic | — | 2017-10-10 |
| 9710349 | Storing first computer trace information in memory of second computer | Karthik Ramana Sankar | 2017-07-18 |
| 9684583 | Trace data export to remote memory using memory mapped write transactions | Karthik Ramana Sankar | 2017-06-20 |
| 9639447 | Trace data export to remote memory using remotely generated reads | Karthik Ramana Sankar | 2017-05-02 |
| 9633213 | Secure emulation logic between page attribute table and test interface | — | 2017-04-25 |
| 9612283 | Blocking the effects of scan chain testing upon a change in scan chain topology | Robert A. McGowan | 2017-04-04 |