Issued Patents All Time
Showing 25 most recent of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12355586 | Scalable virtualized controller area network system | Arun Kumar Barman, Pradeep Singh, Rahul Agrawal, Devendra Singh | 2025-07-08 |
| 12314192 | Multiple level SoC resource allocation and isolation system and method | — | 2025-05-27 |
| 11755361 | Freedom from interference for aggregated communication channel handling using event-based processor extensions | Brian C. Kahne, Michael A. Fischer | 2023-09-12 |
| 10048314 | Scan path only one-bit scan register when component not selected | Gary L. Swoboda | 2018-08-14 |
| 9903912 | Status register between test data I/O of scan port SUT | Gary L. Swoboda | 2018-02-27 |
| 9626279 | Debug method and device for providing indexed trace messages | Robert N. Ehrlich | 2017-04-18 |
| 9626280 | Debug method and device for handling exceptions and interrupts | Robert N. Ehrlich, Michael Brian SCHINZLER | 2017-04-18 |
| 9612283 | Blocking the effects of scan chain testing upon a change in scan chain topology | Gary L. Swoboda | 2017-04-04 |
| 9495169 | Predicate trace compression | Robert N. Ehrlich, Petru Lauric | 2016-11-15 |
| 9395413 | Blocking the effects of scan chain testing upon a change in scan chain topology | Gary L. Swoboda | 2016-07-19 |
| 9304880 | System and method for multicore processing | Michael L. Olivarez, Stephen J. Benzel, Robert N. Ehrlich | 2016-04-05 |
| 9285426 | Blocking the effects of scan chain testing upon a change in scan chain topology | Gary L. Swoboda | 2016-03-15 |
| 9157958 | Blocking the effects of scan chain testing upon a change in scan chain topology | Gary L. Swoboda | 2015-10-13 |
| 9063197 | Blocking the effects of scan chain testing upon a change in scan chain topology | Gary L. Swoboda | 2015-06-23 |
| 8938651 | Blocking the effects of scan chain testing upon a change in scan chain topology | Gary L. Swoboda | 2015-01-20 |
| 8666690 | Heterogeneous multi-core integrated circuit and method for debugging same | Amar Nath Deogharia, Robert N. Ehrlich | 2014-03-04 |
| 8656234 | Test port connected to master output of override selection logic | Gary L. Swoboda | 2014-02-18 |
| 8572323 | Cache result register for quick cache information lookup | Robert N. Ehrlich, Kevin C. Heuer | 2013-10-29 |
| 8464111 | Select, override and master override controlling multiplexing TDI and TDO | Gary L. Swoboda | 2013-06-11 |
| 8359502 | TDI multiplexer gating controlled by override selection logic | Gary L. Swoboda | 2013-01-22 |
| 8261143 | Select signal and component override signal controlling multiplexing TDI/TDO | Gary L. Swoboda | 2012-09-04 |
| 8181067 | Apparatus and method for test and debug of a processor/core having advanced power management | — | 2012-05-15 |
| 7890316 | Synchronizing on-chip data processor trace and timing information for export | Gary L. Swoboda | 2011-02-15 |
| 7676698 | Apparatus and method for coupling a plurality of test access ports to external test and debug facility | — | 2010-03-09 |
| 7558984 | Apparatus and method for test and debug of a processor/core having advanced power management | — | 2009-07-07 |