Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6754787 | System and method for terminating lock-step sequences in a multiprocessor system | Robert J. Miller | 2004-06-22 |
| 6560682 | System and method for terminating lock-step sequences in a multiprocessor system | Robert J. Miller | 2003-05-06 |
| 6292860 | Method for preventing deadlock by suspending operation of processors, bridges, and devices | Arthur F. Cochcroft, Jr., Byron L. Reams, Harry Scrivener, III, Bobby W. Batchler | 2001-09-18 |
| 6128677 | System and method for improved transfer of data between multiple processors and I/O bridges | Robert J. Miller | 2000-10-03 |
| 6120535 | Microporous tubular prosthesis | Michael R. Henson, Joe W. Young | 2000-09-19 |
| 6098113 | Apparatus and method for address translation and allocation for a plurality of input/output (I/O) buses to a system bus | Thomas F. Heil, James M. Ottinger, Jeffrey A. Hawkey | 2000-08-01 |
| 6090136 | Self expandable tubular support | Joe W. Young, Michael R. Henson | 2000-07-18 |
| 6073216 | System and method for reliable system shutdown after coherency corruption | James M. Ottinger, Harry Scrivener, III | 2000-06-06 |
| 6058475 | Booting method for multi-processor computer | Bobby W. Batchler | 2000-05-02 |
| 6047316 | Multiprocessor computing apparatus having spin lock fairness | Richard R. Barton, Arthur F. Cochcroft, Jr., Robert J. Miller, Byron L. Reams, Roy M. Stevens +1 more | 2000-04-04 |
| 6026472 | Method and apparatus for determining memory page access information in a non-uniform memory access computer system | Larry C. James, Arthur F. Cochcroft, Jr., Peter Washington | 2000-02-15 |
| 6012127 | Multiprocessor computing apparatus with optional coherency directory | James M. Ottinger, Harry Scrivener, III | 2000-01-04 |
| 5919268 | System for determining the average latency of pending pipelined or split transaction requests through using two counters and logic divider | — | 1999-07-06 |
| 5765195 | Method for distributing interprocessor interrupt requests via cache memory coherency mechanisms | — | 1998-06-09 |
| 5758065 | System and method of establishing error precedence in a computer system | Byron L. Reams | 1998-05-26 |
| 5728150 | Expandable microporous prosthesis | Robert F. Rosenbluth, Rodney Brenneman | 1998-03-17 |
| 5701422 | Method for ensuring cycle ordering requirements within a hierarchical bus system including split-transaction buses | James B. Kirkland, JR. | 1997-12-23 |
| 5676697 | Two-piece, bifurcated intraluminal graft for repair of aneurysm | — | 1997-10-14 |
| 5418914 | Retry scheme for controlling transactions between two busses | Thomas F. Heil, Gene F. Young, Craig A. Walrath, James M. Ottinger, Marti D. Miller | 1995-05-23 |
| 5359715 | Architectures for computer systems having multiple processors, multiple system buses and multiple I/O buses interfaced via multiple ported interfaces | Thomas F. Heil, Craig A. Walrath, Jimmy D. Pike, Arthur F. Cochcroft, Jr., P. Chris Raeuber +2 more | 1994-10-25 |
| 5327540 | Method and apparatus for decoding bus master arbitration levels to optimize memory transfers | Thomas F. Heil, Daniel C. Robbins | 1994-07-05 |
| 5269005 | Method and apparatus for transferring data within a computer system | Thomas F. Heil, Gene F. Young | 1993-12-07 |