Issued Patents All Time
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9817749 | Apparatus and method of offloading processing from a data storage device to a host device | Manuel Antonio D'Abreu | 2017-11-14 |
| 9406346 | Smart bridge for memory core | Manuel Antonio D'Abreu, Stephen Skala, Radhakrishnan Nair, Deepak Pancholi | 2016-08-02 |
| 9406385 | Apparatus and method of storing data at a multi-bit storage element | Manuel Antonio D'Abreu | 2016-08-02 |
| 9361220 | Apparatus and method of using dummy data while storing data at a multi-bit storage element | Manuel Antonio D'Abreu | 2016-06-07 |
| 9245631 | Apparatus and method of storing data at a multi-bit storage element | Manuel Antonio D'Abreu | 2016-01-26 |
| 9218852 | Smart bridge for memory core | Manuel Antonio D'Abreu, Stephen Skala, Radhakrishnan Nair, Deepak Pancholi | 2015-12-22 |
| 9177609 | Smart bridge for memory core | Manuel Antonio D'Abreu, Stephen Skala, Radhakrishnan Nair, Deepak Pancholi | 2015-11-03 |
| 9177611 | Smart bridge for memory core | Manuel Antonio D'Abreu, Stephen Skala, Radhakrishnan Nair, Deepak Pancholi | 2015-11-03 |
| 9177610 | Smart bridge for memory core | Manuel Antonio D'Abreu, Stephen Skala, Radhakrishnan Nair, Deepak Pancholi | 2015-11-03 |
| 9177612 | Smart bridge for memory core | Manuel Antonio D'Abreu, Stephen Skala, Radhakrishnan Nair, Deepak Pancholi | 2015-11-03 |
| 9153331 | Tracking cell erase counts of non-volatile memory | Manuel Antonio D'Abreu, Stephen Skala | 2015-10-06 |
| 9142261 | Smart bridge for memory core | Manuel Antonio D'Abreu, Stephen Skala, Radhakrishnan Nair, Deepak Pancholi | 2015-09-22 |
| 9129689 | Tracking erase pulses for non-volatile memory | Manuel Antonio D'Abreu, Stephen Skala | 2015-09-08 |
| 9117533 | Tracking erase operations to regions of non-volatile memory | Manuel Antonio D'Abreu, Stephen Skala | 2015-08-25 |
| 9110788 | Apparatus and method of using dummy data while storing data at a multi-bit storage element | Manuel Antonio D'Abreu | 2015-08-18 |
| 8838883 | System and method of adjusting a programming step size for a block of a memory | Manuel Antonio D'Abreu, Stephen Skala | 2014-09-16 |
| 8737130 | System and method of determining a programming step size for a word line of a memory | Manuel Antonio D'Abreu, Stephen Skala | 2014-05-27 |
| 7343510 | Method and device for selecting one of multiple clock signals based on frequency differences of such clock signals | Mark A. Ross, S. Babar Raza, Anup Nayak, Walter F. Bridgewater | 2008-03-11 |
| 7225283 | Asynchronous arbiter with bounded resolution time and predictable output state | Anup Nayak, Fariborz Golshani, Derwin W. Mattos | 2007-05-29 |
| 7184359 | System and method for staging concurrent accesses to a memory address location via a single port using a high speed sampling clock | Walter F. Bridgewater, Anup Nayak, S. Babar Raza | 2007-02-27 |
| 7032083 | Glitch-free memory address decoding circuits and methods and memory subsystems using the same | Robert A. Jensen, Mail Khoi, Vikram Shenoy | 2006-04-18 |
| 6757852 | Self resetting high speed redundancy circuit and method thereof | Hamed Ghassemi, Wai T. Lau | 2004-06-29 |
| 6507222 | High speed single ended sense amplifier | Robert A. Jensen | 2003-01-14 |
| 6501692 | Circuit and method for stress testing a static random access memory (SRAM) device | John L. Melanson, Robert A. Jensen, Vikram Shenoy | 2002-12-31 |
| 6275070 | Integrated circuit having a high speed clock input buffer | Wai T. Lau | 2001-08-14 |