| 6385670 |
Data compression or decompressions during DMA transfer between a source and a destination by independently controlling the incrementing of a source and a destination address registers |
Melanie D. Typaldos |
2002-05-07 |
| 6298396 |
System for loading a current buffer desciptor register with a value different from current value to cause a previously read buffer descriptor to be read again |
Bruce A. Loyer, Thai H. Pham |
2001-10-02 |
| 6263460 |
Microcontroller architecture and associated method providing for testing of an on-chip memory device |
Robert I. Pinkerton, Jr. |
2001-07-17 |
| 6260162 |
Test mode programmable reset for a watchdog timer |
Melanie D. Typaldos, Martin Schuessler |
2001-07-10 |
| 6182165 |
Staggered polling of buffer descriptors in a buffer descriptor ring direct memory access system |
— |
2001-01-30 |
| 5748640 |
Technique for incorporating a built-in self-test (BIST) of a DRAM block with existing functional test vectors for a microprocessor |
Chongjun Jiang, Timothy J. Baldwin, Robert D. Bryfogle, Bobby I. Pinkerton, Jr. |
1998-05-05 |
| 5668815 |
Method for testing integrated memory using an integrated DMA controller |
Robert Paul Gittinger |
1997-09-16 |