| 6850561 |
Predictable updating of a baud divisor of an asynchronous serial port during data reception |
Bruce A. Loyer, Hock Koon Lee |
2005-02-01 |
| 6385670 |
Data compression or decompressions during DMA transfer between a source and a destination by independently controlling the incrementing of a source and a destination address registers |
David A. Spilo |
2002-05-07 |
| 6366610 |
Autobauding with adjustment to a programmable baud rate |
Bruce A. Loyer |
2002-04-02 |
| 6332173 |
UART automatic parity support for frames with address bits |
— |
2001-12-18 |
| 6311235 |
UART support for address bit on seven bit frames |
— |
2001-10-30 |
| 6260162 |
Test mode programmable reset for a watchdog timer |
David A. Spilo, Martin Schuessler |
2001-07-10 |
| 6145103 |
Emulator support mode for disabling and reconfiguring timeouts of a watchdog timer |
Patrick Maupin |
2000-11-07 |
| 6105081 |
UART character matching used for address matching on a register-by-register basis |
— |
2000-08-15 |
| 5978865 |
System for performing DMA transfers where an interrupt request signal is generated based on the value of the last of a plurality of data bits transmitted |
John P. Hansen, Ronald W. Stence |
1999-11-02 |
| 5958024 |
System having a receive data register for storing at least nine data bits of frame and status bits indicating the status of asynchronous serial receiver |
Patrick Maupin |
1999-09-28 |
| 5896549 |
System for selecting between internal and external DMA request where ASP generates internal request is determined by at least one bit position within configuration register |
John P. Hansen, Louis R. Stott |
1999-04-20 |
| 5862148 |
Microcontroller with improved debug capability for internal memory |
Eric G. Chambers, Wade Williams |
1999-01-19 |