Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6745370 | Method for selecting an optimal level of redundancy in the design of memories | Julie Segal, John Caywood | 2004-06-01 |
| 6330696 | Self-testing of DRAMs for multiple faults | Yervant Zorian | 2001-12-11 |
| 6154714 | Method for using wafer navigation to reduce testing times of integrated circuit wafers | — | 2000-11-28 |
| 6096093 | Method for using inspection data for improving throughput of stepper operations in manufacturing of integrated circuits | John Caywood | 2000-08-01 |