Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12150254 | Method of forming a laminate structure having a plated through-hole using a removable cover layer | Shinichi Iketani | 2024-11-19 |
| 11765827 | Simultaneous and selective wide gap partitioning of via structures using plating resist | Shinichi Iketani, George Dudnikov | 2023-09-19 |
| 11399439 | Methods of forming high aspect ratio plated through holes and high precision stub removal in a printed circuit board | Douglas Ward Thomas, Shinichi Iketani | 2022-07-26 |
| 11246226 | Laminate structures with hole plugs and methods of forming laminate structures with hole plugs | Shinichi Iketani | 2022-02-08 |
| 10757819 | Method of forming a laminate structure having a plated through-hole using a removable cover layer | Shinichi Iketani | 2020-08-25 |
| 10667390 | Simultaneous and selective wide gap partitioning of via structures using plating resist | Shinichi Iketani, George Dudnikov | 2020-05-26 |
| 10362687 | Simultaneous and selective wide gap partitioning of via structures using plating resist | Shinichi Iketani | 2019-07-23 |
| 10237983 | Method for forming hole plug | Shinichi Iketani | 2019-03-19 |
| 10188001 | Methods of forming high aspect ratio plated through holes and high precision stub removal in a printed circuit board | Douglas Ward Thomas, Shinichi Iketani | 2019-01-22 |
| 10123432 | Simultaneous and selective wide gap partitioning of via structures using plating resist | Shinichi Iketani | 2018-11-06 |
| 9781830 | Simultaneous and selective wide gap partitioning of via structures using plating resist | Shinichi Iketani, George Dudnikov | 2017-10-03 |
| 9781844 | Simultaneous and selective wide gap partitioning of via structures using plating resist | Shinichi Iketani | 2017-10-03 |