Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11442297 | Perovskite oxides with a-axis orientation | — | 2022-09-13 |
| 10930750 | Method for forming a qubit device | Nadine Collaert | 2021-02-23 |
| 10872824 | Si-based high-mobility CMOS device with stacked channel layers and resulting devices | Guillaume Boccardi | 2020-12-22 |
| 10763643 | Laser devices | Joris Van Campenhout, Maria Ioanna Pantouvaki, Ashwyn Srinivasan, Irina Kulkova | 2020-09-01 |
| 10354868 | Method for formation of a transition metal dichalcogenide (TMDC) material layer | Salim El Kazzi | 2019-07-16 |
| 10256157 | Method for manufacturing a Si-based high-mobility CMOS device with stacked channel layers, and resulting devices | Guillaume Boccardi | 2019-04-09 |
| 10128371 | Self-aligned nanostructures for semiconductor devices | Boon Teik Chan, Zheng Tao | 2018-11-13 |
| 9947591 | Method for manufacturing a Si-based high-mobility CMOS device with stacked channel layers, and resulting devices | Guillaume Boccardi | 2018-04-17 |
| 9601488 | Gate-all-around semiconductor device and method of fabricating the same | Niamh Waldron, Nadine Collaert | 2017-03-21 |
| 9478611 | Vertical nanowire semiconductor structures | Boon Teik Chan | 2016-10-25 |
| 9425314 | Passivated III-V or Ge fin-shaped field effect transistor | Matty Caymax | 2016-08-23 |
| 9419110 | Method for reducing contact resistance in MOS | Nadine Collaert | 2016-08-16 |
| 9324818 | Gate-all-around semiconductor device and method of fabricating the same | Niamh Waldron, Nadine Collaert | 2016-04-26 |
| 9082616 | III-V device and method for manufacturing thereof | — | 2015-07-14 |
| 8994109 | High-K heterostructure | Mario El-Kazzi, Guillaume Saint-Girons, Guy Hollinger | 2015-03-31 |
| 8872238 | Method for manufacturing a low defect interface between a dielectric and a III-V compound | — | 2014-10-28 |
| 8426261 | High-k heterostructure | Mario El-Kazzi, Guillaume Saint-Girons, Guy Hollinger | 2013-04-23 |
| 8314017 | Method for manufacturing a low defect interface between a dielectric and a III-V compound | — | 2012-11-20 |
| 8232581 | Method for manufacturing an III-V engineered substrate and the III-V engineered substrate thereof | Geoffrey Pourtois, Guy Brammertz, Matty Caymax | 2012-07-31 |