CP

Chetan Paragaonkar

PM Pmc-Sierra: 2 patents #31 of 145Top 25%
CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
Overall (All Time): #1,439,572 of 4,157,543Top 35%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
11128410 Hardware-efficient scheduling of packets on data paths Gopi Krishnamurthy, Anish Mathew, Raveendra Pai Gopalakrishna, Anujan Varma 2021-09-21
8782295 Method and apparatus for a multi-engine descriptor controller for distributing data processing tasks across the engines Kuan Hua Tan 2014-07-15
8601169 Method and apparatus for a multi-engine descriptor controller for distributing data processing tasks across the engines Kuan Hua Tan 2013-12-03