| 6980211 |
Automatic schematic diagram generation using topology information |
Shyh-Chang Lin, Yu-Sheng Lu, Bang-Hwa Ho |
2005-12-27 |
| 6546526 |
Active trace debugging for hardware description languages |
Ming-Chih Lai, Bang-Hwa Ho, Jien-Shen Tsai |
2003-04-08 |
| 6446243 |
Method for functional verification of VLSI circuit designs utilizing reusable functional blocks or intellectual property cores |
Yen-Son Paul Huang, Changson Teng |
2002-09-03 |
| 6366874 |
System and method for browsing graphically an electronic design based on a hardware description language specification |
Jensen Tsai, Meng-Hui Chen, Banghwa Ho, Yen-Son Paul Huang, Changson Teng |
2002-04-02 |
| 6321363 |
Incremental simulation using previous simulation results and knowledge of changes to simulation model to achieve fast simulation time |
Yen-Son Paul Huang, Martin Lu, Jensen Tsai |
2001-11-20 |