Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12245415 | Method of manufacturing semiconductor device having protrusion of word line | — | 2025-03-04 |
| 12178035 | Semiconductor device having protrusion of word line | — | 2024-12-24 |
| 12014986 | Method for preparing semiconductor device structure with conductive plugs of different aspect ratios and manganese-containing lining layer | — | 2024-06-18 |
| 11895826 | Method for preparing semiconductor device structure with air gap | — | 2024-02-06 |
| 11646268 | Semiconductor device structure with conductive plugs of different aspect ratios and manganese-containing liner having different thicknesses | — | 2023-05-09 |
| 11587885 | Method for fabricating semiconductor device with EMI protection structure | — | 2023-02-21 |
| 11417608 | Semiconductor device with EMI protection structure and method for fabricating the same | — | 2022-08-16 |
| 11417726 | Semiconductor structure having air gap dielectric | — | 2022-08-16 |
| 11217591 | Semiconductor device structure with air gap and method for preparing the same | — | 2022-01-04 |
| 11049715 | Method for manufacturing a semiconductor structure | — | 2021-06-29 |
| 10957760 | Semiconductor structure having air gap dielectric and method of preparing the same | — | 2021-03-23 |
| 9093471 | Method for forming trench MOS structure | Yi-Nan Chen, Hsien-Wen Liu | 2015-07-28 |
| 8912595 | Trench MOS structure and method for forming the same | Yi-Nan Chen, Hsien-Wen Liu | 2014-12-16 |
| 8816715 | MOS test structure, method for forming MOS test structure and method for performing wafer acceptance test | Yi-Nan Chen, Hsien-Wen Liu | 2014-08-26 |
| 8692318 | Trench MOS structure and method for making the same | Yi-Nan Chen, Hsien-Wen Liu | 2014-04-08 |