| 10607982 |
Layout connection isolation technique for improving immunity to jitter and voltage drop in a standard cell |
Matthew Berzins |
2020-03-31 |
| 8289060 |
Pulsed state retention power gating flip-flop |
Samuel J. Tower, Matthew Berzins |
2012-10-16 |
| 7826581 |
Linearized digital phase-locked loop method for maintaining end of packet time linearity |
Stephen M. Prather, Matthew Berzins, Steven P. Larky, Joseph A. Cetin |
2010-11-02 |
| 7683697 |
Circuitry and method for buffering a power mode control signal |
Matthew Berzins, Andrew Paul Hoover |
2010-03-23 |
| 7583121 |
Flip-flop having logic state retention during a power down mode and method therefor |
Matthew Berzins, Samuel J. Tower |
2009-09-01 |
| 7394293 |
Circuit and method for rapid power up of a differential output driver |
Jeffrey Waldrip, Stephen M. Prather, Matthew Berzins |
2008-07-01 |
| 7239178 |
Circuit and method for CMOS voltage level translation |
Matthew Berzins, Stephen M. Prather |
2007-07-03 |
| 7176720 |
Low duty cycle distortion differential to CMOS translator |
Stephen M. Prather, Jeffrey Waldrip, Matthew Berzins |
2007-02-13 |
| 6781465 |
Method and apparatus for differential signal detection |
Matthew Berzins, Stephen M. Prather |
2004-08-24 |
| 6683818 |
Asynchronous random access memory with power optimizing clock |
Mathew S. Berzins, Steven P. Larky |
2004-01-27 |
