Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5715427 | Semi-associative cache with MRU/LRU replacement | David D. Barrera, Paul C. Rossbach | 1998-02-03 |
| 5550995 | Memory cache with automatic alliased entry invalidation and method of operation | David D. Barrera, Paul C. Rossbach | 1996-08-27 |
| 5499204 | Memory cache with interlaced data and method of operation | David D. Barrera, Dave S. Levitan, Paul C. Rossbach | 1996-03-12 |
| 5428632 | Control circuit for dual port memory | — | 1995-06-27 |
| 5422591 | Output driver circuit with body bias control for multiple power supply operation | William C. Slemmer | 1995-06-06 |
| 5339322 | Cache tag parity detect circuit | — | 1994-08-16 |
| 5319768 | Control circuit for resetting a snoop valid bit in a dual port cache tag memory | — | 1994-06-07 |
| 5311477 | Integrated circuit memory device having flash clear | — | 1994-05-10 |
| 5297094 | Integrated circuit memory device with redundant rows | — | 1994-03-22 |
| 5287322 | Integrated circuit dual-port memory device having reduced capacitance | — | 1994-02-15 |