Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8631376 | Method and system for generating a placement layout of a VLSI circuit design | Tobias Werner, Raphael Polig, Alexander Woerner | 2014-01-14 |
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8631376 | Method and system for generating a placement layout of a VLSI circuit design | Tobias Werner, Raphael Polig, Alexander Woerner | 2014-01-14 |