Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7480878 | Method and system for layout versus schematic validation of integrated circuit designs | Viswanathan Lakshmanan, Brent Wray Acott | 2009-01-20 |
| 7149989 | Method of early physical design validation and identification of texted metal short circuits in an integrated circuit design | Viswanathan Lakshmanan, Lisa M. Miller, Jonathan P. Kuppinger | 2006-12-12 |