Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11621043 | Read level tracking and optimization | Richard David Barndt, Richard Leo Galbraith, Jonas Goode, Niranjay Ravindran, Anthony Dwayne Weathers | 2023-04-04 |
| 11190218 | Code rate switching mechanism for data storage system | Aniryudh Reddy Durgam | 2021-11-30 |
| 11101006 | Read level tracking and optimization | Richard David Barndt, Richard Leo Galbraith, Jonas Goode, Niranjay Ravindran, Anthony Dwayne Weathers | 2021-08-24 |
| 10748628 | Read level tracking and optimization | Richard David Barndt, Richard Leo Galbraith, Jonas Goode, Niranjay Ravindran, Anthony Dwayne Weathers | 2020-08-18 |
| 10644727 | Code rate switching mechanism for flash memory | Aniryudh Reddy Durgam | 2020-05-05 |
| 10545810 | Method and apparatus for monitoring non-volatile memory read errors using background media scan | Richard David Barndt, Hung-min Chang, Jerry Lo, Hung-Cheng Yeh | 2020-01-28 |
| 10496334 | Solid state drive using two-level indirection architecture | Mark Myran, Chandan Mishra, Amir Hossein Gholamipour, Namhoon Yoo | 2019-12-03 |
| 10373695 | Methods and apparatus for read disturb detection and handling | Richard David Barndt, Haining Liu, Jerry Lo | 2019-08-06 |
| 10282111 | Adaptive wear levelling | Richard David Barndt, Scott Kayser | 2019-05-07 |
| 10236070 | Read level tracking and optimization | Richard David Barndt, Richard Leo Galbraith, Jonas Goode, Niranjay Ravindran, Anthony Dwayne Weathers | 2019-03-19 |
| 9761308 | Systems and methods for adaptive read level adjustment | — | 2017-09-12 |
| 9377962 | Determining bias information for offsetting operating variations in memory cells | Pablo A. Ziperovich | 2016-06-28 |
| 9270296 | Method and system for soft decoding through single read | Majid Nemati Anaraki | 2016-02-23 |
| 9224456 | Setting operating parameters for memory cells based on wordline address and cycle information | Pablo A. Ziperovich | 2015-12-29 |
| 9195586 | Determining bias information for offsetting operating variations in memory cells based on wordline address | Pablo A. Ziperovich | 2015-11-24 |
| 9047955 | Adjusting operating parameters for memory cells based on wordline address and cycle information | Pablo A. Ziperovich | 2015-06-02 |
| 9007854 | Method and system for optimized soft decoding in a data storage device | Majid Nemati Anaraki | 2015-04-14 |
| 8737136 | Apparatus and method for determining a read level of a memory cell based on cycle information | — | 2014-05-27 |
| 8644099 | Apparatus and method for determining a read level of a flash memory after an inactive period of time | Lun Bin Huang, Ashot Melik-Martirosian | 2014-02-04 |
| RE38045 | Data compensation/resynchronization circuit for phase lock loops | R. Frank O'Bleness | 2003-03-25 |
| 5777498 | Data compensation/resynchronization circuit for phase lock loops | R. Frank O'Bleness | 1998-07-07 |