Issued Patents All Time
Showing 25 most recent of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12430130 | Floating point norm instruction | Mrudula Gore | 2025-09-30 |
| 12399717 | Processing device for intermediate value scaling | Simon Knowles, Stephen Felix, Carlo Luschi, Badreddine Noune, Mrudula Gore +3 more | 2025-08-26 |
| 12367043 | Multi-threaded barrel processor using shared weight registers in a common weights register file | Simon Knowles, Mrudula Gore | 2025-07-22 |
| 12141092 | Instruction set | Simon Knowles, Daniel John Pelham Wilkinson, Richard Luke Southwell Osborne, Stephen Felix, Jonathan Mangnall +1 more | 2024-11-12 |
| 12124699 | Processing device for handling misaligned data | Edward A. Andrews, Peter Hedinger | 2024-10-22 |
| 12112164 | Machine code instruction | Simon Knowles, Godfrey Da Costa, Badreddine Noune | 2024-10-08 |
| 12013781 | Processing device using variable stride pattern | Sam Chesney, Richard Luke Southwell Osborne, Edward A. Andrews | 2024-06-18 |
| 11966740 | Use of multiple different variants of floating point number formats in floating point operations on a per-operand basis | Mrudula Gore | 2024-04-23 |
| 11928523 | Synchronisation for a multi-tile processing unit | Simon Knowles, Daniel John Pelham Wilkinson, Stephen Felix, Richard Luke Southwell Osborne, David Lacey +1 more | 2024-03-12 |
| 11893390 | Method of debugging a processor that executes vertices of an application, each vertex being assigned to a programming thread of the processor | Richard Luke Southwell Osborne, Matthew David Fyles | 2024-02-06 |
| 11775415 | Debugging instruction register to receive and input debugging instructions to a processor for a thread of execution in a debug mode | Graham Bernard Cunningham | 2023-10-03 |
| 11709794 | Exchange between stacked die | Stephen Felix, Richard Luke Southwell Osborne | 2023-07-25 |
| 11645081 | Handling exceptions in a multi-tile processing arrangement | Matthew David Fyles | 2023-05-09 |
| 11593185 | Synchronization in a multi-tile processing arrangement | Simon Knowles | 2023-02-28 |
| 11586483 | Synchronization amongst processor tiles | Daniel John Pelham Wilkinson, Simon Knowles, Matthew David Fyles, Stephen Felix | 2023-02-21 |
| 11567768 | Repeat instruction for loading and/or executing code in a claimable repeat cache a specified number of times | Simon Knowles, Mrudula Gore, Jonathan Ferguson | 2023-01-31 |
| 11467833 | Load-store instruction for performing multiple loads, a store, and strided increment of multiple addresses | Simon Knowles, Mrudula Gore | 2022-10-11 |
| 11449338 | Handling exceptions in a multi-tile processing arrangement | Matthew David Fyles | 2022-09-20 |
| 11416440 | Controlling timing in computer processing | Richard Luke Southwell Osborne, Stephen Felix | 2022-08-16 |
| 11416258 | Method of debugging a processor that executes vertices of an application, each vertex being assigned to a programming thread of the processor | Richard Luke Southwell Osborne, Matthew David Fyles | 2022-08-16 |
| 11321272 | Instruction set | Simon Knowles, Daniel John Pelham Wilkinson, Richard Luke Southwell Osborne, Stephen Felix, Jonathan Mangnall +1 more | 2022-05-03 |
| 11262787 | Compiler method | Simon Knowles, Daniel John Pelham Wilkinson, Richard Luke Southwell Osborne, Stephen Felix, Jonathan Mangnall +1 more | 2022-03-01 |
| 11169778 | Converting floating point numbers to reduce the precision | Stephen Felix, Mrudula Gore | 2021-11-09 |
| 11169777 | Multiple modes for handling overflow conditions resulting from arithmetic operations | Edward A. Andrews, Stephen Felix, Mrudula Gore | 2021-11-09 |
| 11061679 | Double-load instruction using a fixed stride and a variable stride for updating addresses between successive instructions | Simon Knowles, Mrudula Gore | 2021-07-13 |