Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12376403 | Low-refractivity grid structure and method forming same | Kun-Huei Lin, Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee | 2025-07-29 |
| 11728364 | Low-refractivity grid structure and method forming same | Kun-Huei Lin, Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee | 2023-08-15 |
| 10061898 | Avatar-based charting method and system for assisted diagnosis | Ying-Fong Huang, Jer-Chia Tsai, Jer-Min Tsai, Yu-Hsien Chiu, I-Te Chen | 2018-08-28 |
| 9558108 | Half block management for flash storage devices | Yu-Ming Chang, Yung-Chun Li, Hsing-Chen Lu, Hsiang-Pang Li, Yuan-Hao Chang +1 more | 2017-01-31 |
| 9547586 | Metadata containers with indirect pointers | Hung-Sheng Chang, Hsiang-Pang Li, Yuan-Hao Chang, Pi-Cheng Hsiu, Tei-Wei Kuo | 2017-01-17 |
| 9501396 | Wear leveling with marching strategy | Hung-Sheng Chang, Hsiang-Pang Li, Yuan-Hao Chang, Pi-Cheng Hsiu, Tei-Wei Kuo | 2016-11-22 |
| 9251056 | Bucket-based wear leveling method and apparatus | Po-Chao Fang, Hsiang-Pang Li, Chi-Hao Chen, Pi-Cheng Hsiu, Tei-Wei Kuo | 2016-02-02 |
| 9171616 | Memory with multiple levels of data retention | Ren-Shuo Liu, De-Yu Shen, Chia-Lin Yang, Ye LIN | 2015-10-27 |
| 9025375 | Memory disturb reduction for nonvolatile memory | Yu-Ming Chang, Yung-Chun Li, Hsing-Chen Lu, Hsiang-Pang Li, Yuan-Hao Chang +1 more | 2015-05-05 |
| 8987787 | Semiconductor structure and method for manufacturing the same | Shih-Hung Chen, Kuang Yeu Hsieh | 2015-03-24 |
| 8769189 | Method and apparatus for byte-access in block-based flash memory | Hsiang-Pang Li, Chung-Jae Doong | 2014-07-01 |
| 7554844 | Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency | Carl W. Werner, Andreas Haeberli, Leon Sea Jiunn Wong, Hock C. So, Sau C. Wong | 2009-06-30 |
| 7298670 | Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency | Carl W. Werner, Andreas Haeberli, Leon Sea Jiunn Wong, Hock C. So, Sau C. Wong | 2007-11-20 |
| 7106632 | Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency | Carl W. Werner, Andreas Haeberli, Leon Sea Jiunn Wong, Hock C. So, Sau C. Wong | 2006-09-12 |
| 6760262 | Charge pump circuit adjustable in response to an external voltage source | Andreas Haeberli, Sau C. Wong, Hock C. So, Carl W. Werner, Leon Sea Jiunn Wong | 2004-07-06 |
| 6556465 | Adjustable circuits for analog or multi-level memory | Andreas Haeberli, Sau C. Wong, Hock C. So, Carl W. Werner, Leon Sea Jiunn Wong | 2003-04-29 |
| 6549456 | Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency | Carl W. Werner, Andreas Haeberli, Leon Sea Jiunn Wong, Hock C. So, Sau C. Wong | 2003-04-15 |
| 6370075 | Charge pump circuit adjustable in response to an external voltage source | Andreas Haeberli, Sau C. Wong, Hock C. So, Carl W. Werner, Leon Sea Jiunn Wong | 2002-04-09 |
| 6345000 | Flash memory permitting simultaneous read/write and erase operations in a single memory array | Sau C. Wong, Hock C. So, Roger Y. Lo | 2002-02-05 |
| 6208542 | Techniques for storing digital data in an analog or multilevel memory | Andreas Haeberli, Carl W. Werner, Sau C. Wong, Hock C. So, Leon Sea Jiunn Wong | 2001-03-27 |
| 6184726 | Adjustable level shifter circuits for analog or multilevel memories | Andreas Haeberli, Carl W. Werner, Hock C. So, Leon Sea Jiunn Wong, Sau C. Wong | 2001-02-06 |
| 6185119 | Analog memory IC with fully differential signal path | Andreas Haeberli, Carl W. Werner, Hock C. So, Sau C. Wong, Leon Sea Jiunn Wong | 2001-02-06 |
| 6034541 | In-system programmable interconnect circuit | Stanley J. Kopec, Jr., Jerome C. Farmer, Cyrus Y. Tsui | 2000-03-07 |
| 5341048 | Clock invert and select circuit | Hiten S. Randhawa | 1994-08-23 |