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Digitally controlled delay lines with fine grain and coarse grain delay elements, and methods and systems to adjust in fine grain increments |
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2013-10-22 |
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Extracting aligned data from two source registers without shifting by executing coprocessor instruction with mode bit for deriving offset from immediate or register |
Nigel C. Paver, Murli Ganeshan |
2008-04-08 |
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Coprocessor processing instruction with coprocessor ID to broadcast main processor register data element to coprocessor multi-element register |
Nigel C. Paver, Murli Ganeshan |
2006-05-16 |
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Conditional execution of coprocessor instruction based on main processor arithmetic flags |
Nigel C. Paver, William T. Maghielse, Jianwei Liu, Anthony Jebson, Kailesh B. Bavaria +6 more |
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Phase-locked loop arrangement with fast lock mode |
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2002-04-16 |
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Sectional column activated memory |
— |
2001-05-01 |
