Issued Patents All Time
Showing 126–142 of 142 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6724222 | Programmable logic with lower internal voltage circuitry | Rakesh Patel, John E. Turner, John Lam | 2004-04-20 |
| 6583646 | Overvoltage-tolerant interface for integrated circuits | Rakesh Patel, John E. Turner | 2003-06-24 |
| 6563343 | Circuitry for a low internal voltage | Rakesh Patel, John E. Turner, John Lam | 2003-05-13 |
| 6433585 | Overvoltage-tolerant interface for integrated circuits | Rakesh Patel, John E. Turner | 2002-08-13 |
| 6414518 | Circuitry for a low internal voltage integrated circuit | Rakesh Patel, John E. Turner, John Lam | 2002-07-02 |
| 6265926 | Programmable PCI overvoltage input clamp | — | 2001-07-24 |
| 6252422 | Overvoltage-tolerant interface for intergrated circuits | Rakesh Patel, John E. Turner | 2001-06-26 |
| 6147511 | Overvoltage-tolerant interface for integrated circuits | Rakesh Patel, John E. Turner | 2000-11-14 |
| 6137313 | Resistive pull-up device for I/O pin | Thomas H. White | 2000-10-24 |
| 6107854 | Variable speed path circuit and method | John E. Turner, Thomas H. White, Rakesh Patel | 2000-08-22 |
| 6025737 | Circuitry for a low internal voltage integrated circuit | Rakesh Patel, John E. Turner, John Lam | 2000-02-15 |
| 5693540 | Method of fabricating integrated circuits | John E. Turner, Kevin A. Norman, Thomas H. White | 1997-12-02 |
| 4477879 | Floating point processor architecture which performs square root by hardware | — | 1984-10-16 |
| 4336599 | Circuit for performing a square root calculation | — | 1982-06-22 |
| 4334284 | Multiplier decoding using parallel MQ register | — | 1982-06-08 |
| 4282582 | Floating point processor architecture which performs subtraction with reduced number of guard bits | — | 1981-08-04 |
| 4276607 | Multiplier circuit which detects and skips over trailing zeros | — | 1981-06-30 |