Issued Patents All Time
Showing 76–100 of 316 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10587395 | Architecture and instruction set for implementing advanced encryption standard (AES) | Shay Gueron, Wajdi K. Feghali | 2020-03-10 |
| 10581594 | Instructions processors, methods, and systems to process secure hash algorithms | Gilbert M. Wolrich, Kirk S. Yap, James D. Guilford | 2020-03-03 |
| 10581590 | Flexible architecture and instruction for advanced encryption standard (AES) | Shay Gueron, Wajdi K. Feghali, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty +1 more | 2020-03-03 |
| 10579380 | System-on-chip (SoC) to perform a bit range isolation instruction | Maxim Loktyukhin, Eric W. Mahurin, Bret L. Toll, Martin G. Dixon, Sean P. Mirkes +2 more | 2020-03-03 |
| 10579379 | Processor to perform a bit range isolation instruction | Maxim Loktyukhin, Eric W. Mahurin, Bret L. Toll, Martin G. Dixon, Sean P. Mirkes +2 more | 2020-03-03 |
| 10567161 | Architecture and instruction set for implementing advanced encryption standard AES | Shay Gueron, Wajdi K. Feghali | 2020-02-18 |
| 10567160 | Architecture and instruction set for implementing advanced encryption standard (AES) | Shay Gueron, Wajdi K. Feghali | 2020-02-18 |
| 10565133 | Techniques for reducing accelerator-memory access costs in platforms with multiple memory channels | — | 2020-02-18 |
| 10560259 | Architecture and instruction set for implementing advanced encryption standard (AES) | Shay Gueron, Wajdi K. Feghali | 2020-02-11 |
| 10560258 | Architecture and instruction set for implementing advanced encryption standard (AES) | Shay Gueron, Wajdi K. Feghali | 2020-02-11 |
| 10554387 | Architecture and instruction set for implementing advanced encryption standard (AES) | Shay Gueron, Wajdi K. Feghali | 2020-02-04 |
| 10554386 | Flexible architecture and instruction for advanced encryption standard (AES) | Shay Gueron, Wajdi K. Feghali, Raghunandan Makaram, Martin G. Dixon, Srinivas Chennupaty +1 more | 2020-02-04 |
| 10528539 | Optimized selection of hash collision chains | James D. Guilford, Daniel F. Cutter | 2020-01-07 |
| 10509580 | Memory controller and methods for memory compression utilizing a hardware compression engine and a dictionary to indicate a zero value, full match, partial match, or no match | Kirk S. Yap, James D. Guilford, Sean M. Gulley | 2019-12-17 |
| 10509651 | Montgomery multiplication processors, methods, systems, and instructions | — | 2019-12-17 |
| 10503510 | SM3 hash function message expansion processors, methods, systems, and instructions | Gilbert M. Wolrich, Kirk S. Yap, Wajdi K. Feghali, Sean M. Gulley | 2019-12-10 |
| 10496703 | Techniques for random operations on compressed data | James D. Guilford | 2019-12-03 |
| 10496373 | Unified integer and carry-less modular multiplier and a reduction circuit | Vikram Suresh, Sanu K. Mathew, Sudhir K. Satpathy | 2019-12-03 |
| 10462110 | System, apparatus and method for providing a unique identifier in a fuseless semiconductor device | Simon N. Peffers, Sean M. Gulley, Sanu K. Mathew | 2019-10-29 |
| 10445261 | System memory having point-to-point link that transports compressed traffic | Kirk S. Yap, Daniel F. Cutter | 2019-10-15 |
| 10437739 | Low-latency accelerator | — | 2019-10-08 |
| 10432393 | Architecture and instruction set for implementing advanced encryption standard (AES) | Shay Gueron, Wajdi K. Feghali | 2019-10-01 |
| 10416900 | Technologies for addressing data in a memory | Jawad B. Khan, Sanjeev N. Trika | 2019-09-17 |
| 10404836 | Managing state data in a compression accelerator | James D. Guilford, Daniel F. Cutter | 2019-09-03 |
| 10379854 | Processor instructions for determining two minimum and two maximum values | James D. Guilford | 2019-08-13 |