Issued Patents All Time
Showing 51–75 of 99 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10530588 | Multi-stage non-linearly cascaded physically unclonable function circuit | Vikram Suresh, Sanu K. Mathew | 2020-01-07 |
| 10496373 | Unified integer and carry-less modular multiplier and a reduction circuit | Vikram Suresh, Sanu K. Mathew, Vinodh Gopal | 2019-12-03 |
| 10498532 | Parallel computation techniques for accelerated cryptographic capabilities | Raghavan Kumar, Sanu K. Mathew, Vikram Suresh | 2019-12-03 |
| 10395035 | Photon emission attack resistance driver circuits | Sanu K. Mathew, Vikram Suresh, Patrick Koeberl | 2019-08-27 |
| 10346343 | Hardware accelerator for platform firmware integrity check | Vikram Suresh, Sanu K. Mathew, Neeraj Upasani | 2019-07-09 |
| 10326596 | Techniques for secure authentication | Vikram Suresh, Sanu K. Mathew | 2019-06-18 |
| 10320414 | Methods and apparatus to parallelize data decompression | Vinodh Gopal, James D. Guilford, Sanu K. Mathew | 2019-06-11 |
| 10313108 | Energy-efficient bitcoin mining hardware accelerators | Vikram Suresh, Sanu K. Mathew | 2019-06-04 |
| 10256973 | Linear masking circuits for side-channel immunization of advanced encryption standard hardware | Raghavan Kumar, Sanu K. Mathew, Avinash L. Varna, Vikram Suresh | 2019-04-09 |
| 10218497 | Hybrid AES-SMS4 hardware accelerator | Vikram Suresh, Sanu K. Mathew | 2019-02-26 |
| 10177782 | Hardware apparatuses and methods for data decompression | James D. Guilford, Sanu K. Mathew, Vinodh Gopal, Vikram Suresh | 2019-01-08 |
| 10164773 | Energy-efficient dual-rail keeperless domino datapath circuits | Vikram Suresh, Sanu K. Mathew | 2018-12-25 |
| 10158485 | Double affine mapped S-box hardware accelerator | Sanu K. Mathew, Vinodh Gopal, Kirk S. Yap | 2018-12-18 |
| 10142098 | Optimized SHA-256 datapath for energy-efficient high-performance Bitcoin mining | Vikram Suresh, Sanu K. Mathew | 2018-11-27 |
| 10135463 | Method and apparatus for accelerating canonical huffman encoding | James D. Guilford, Vinodh Gopal, Kirk S. Yap | 2018-11-20 |
| 10129018 | Hybrid SM3 and SHA acceleration processors | Vikram Suresh, Sanu K. Mathew | 2018-11-13 |
| 10103877 | SMS4 acceleration processors having round constant generation | Sanu K. Mathew, Kirk S. Yap, Vinodh Gopal | 2018-10-16 |
| 10103873 | Power side-channel attack resistant advanced encryption standard accelerator processor | Raghavan Kumar, Sanu K. Mathew, Vikram Suresh | 2018-10-16 |
| 10083034 | Method and apparatus for prefix decoding acceleration | Vinodh Gopal | 2018-09-25 |
| 10042644 | Method and apparatus for speculative decompression | Sanu K. Mathew, Vinodh Gopal, James D. Guilford | 2018-08-07 |
| 10027472 | Non-linear physically unclonable function (PUF) circuit with machine-learning attack resistance | Vikram Suresh, Sanu K. Mathew | 2018-07-17 |
| 10020934 | Hardware accelerator for cryptographic hash operations | Vikram Suresh, Sanu K. Mathew | 2018-07-10 |
| 9996708 | SMS4 acceleration processors having encryption and decryption mapped on a same hardware | Sanu K. Mathew, Kirk S. Yap, Vinodh Gopal | 2018-06-12 |
| 9965248 | Threshold filtering of compressed domain data using steering vector | Sanu K. Mathew, Ram Krishnamurthy | 2018-05-08 |
| 9928036 | Random number generator | Sanu K. Mathew, David Johnston | 2018-03-27 |