SW

Steven Wells

IN Intel: 59 patents #501 of 30,777Top 2%
Kioxia: 11 patents #90 of 1,813Top 5%
Toshiba Memory: 4 patents #468 of 1,971Top 25%
📍 San Jose, CA: #484 of 32,062 inventorsTop 2%
🗺 California: #3,955 of 386,348 inventorsTop 2%
Overall (All Time): #26,236 of 4,157,543Top 1%
74
Patents All Time

Issued Patents All Time

Showing 51–74 of 74 patents

Patent #TitleCo-InventorsDate
5566194 Method and apparatus to improve read reliability in semiconductor memories Neal R. Mielke 1996-10-15
5544119 Method for assuring that an erase process for a memory array has been properly completed Eric J. Magnusson 1996-08-06
5535369 Method for allocating memory in a solid state memory disk Robert Nasry Hasbun, Sara Domonkos, Steven Barbarich 1996-07-09
5515317 Addressing modes for a dynamic single bit per cell to multiple bit per cell memory Kurt B. Robinson 1996-05-07
5490264 Generally-diagonal mapping of address space for row/column organizer memories Mark Winston 1996-02-06
5479633 Method of controlling clean-up of a solid state memory disk storing floating sector data Robert Nasry Hasbun 1995-12-26
5475693 Error management processes for flash EEPROM memory arrays Mark Christopherson, Greg Atwood, Mark E. Bauer, Albert Fazio, Robert Nasry Hasbun 1995-12-12
5473753 Method of managing defects in flash disk memories Eric J. Magnusson, Robert Nasry Hasbun 1995-12-05
5455800 Apparatus and a method for improving the program and erase performance of a flash EEPROM memory array Neal R. Mielke 1995-10-03
5452311 Method and apparatus to improve read reliability in semiconductor memories Neal R. Mielke 1995-09-19
5450363 Gray coding for a multilevel cell memory system Mark Christopherson, Phillip M. L. Kwong 1995-09-12
5448577 Method for reliably storing non-data fields in a flash EEPROM memory array Robert Nasry Hasbun 1995-09-05
5437020 Method and circuitry for detecting lost sectors of data in a solid state memory disk Robert Nasry Hasbun, Richard P. Garner 1995-07-25
5416782 Method and apparatus for improving data failure rate testing for memory arrays Anil Sama 1995-05-16
5369616 Method for assuring that an erase process for a memory array has been properly completed Eric J. Magnusson 1994-11-29
5357475 Method for detaching sectors in a flash EEPROM memory array Robert Nasry Hasbun, Richard P. Garner 1994-10-18
5341330 Method for writing to a flash memory array during erase suspend intervals Mark Winston, Virgil N. Kynett 1994-08-23
5341339 Method for wear leveling in a flash EEPROM memory 1994-08-23
5311462 Physical placement of content addressable memories 1994-05-10
5295113 Flash memory source inhibit generator Patricia L. Dix 1994-03-15
5265059 Circuitry and method for discharging a drain of a cell of a non-volatile semiconductor memory Owen W. Jungroth, Mickey L. Fandrich 1993-11-23
5249158 Flash memory blocking architecture Virgil N. Kynett, Mickey L. Fandrich, Kurt B. Robinson, Owen W. Jungroth 1993-09-28
5222046 Processor controlled command port architecture for flash memory Jerry A. Kreifels, Alan E. Baker, George P. Hoekstra, Virgil N. Kynett, Mark Winston 1993-06-22
5053990 Program/erase selection for flash memory Jerry A. Kreifels, Alan E. Baker, George P. Hoekstra, Virgil N. Kynett, Mark Winston 1991-10-01