Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12235792 | Apparatus and method for temperature-constrained frequency control and scheduling | Jianwei Dai, Somvir Dahiya, Mahesh Kumar P, Stephen H. Gunther, Mark Gallina | 2025-02-25 |
| 11275663 | Fast dynamic capacitance, frequency, and/or voltage throttling apparatus and method | Alexander Gendler, Nimrod Angel, Ameya Ambardekar, Vikas Vij, Tod F. Schiff +1 more | 2022-03-15 |
| 8362806 | Keeper circuit | Clifford L. Ong, Hans J. Greub, Anandraj Devarajan | 2013-01-29 |
| 8320203 | Method and system to lower the minimum operating voltage of register files | Seung H. Hwang | 2012-11-27 |
| 7952941 | Method and apparatus for reducing leakage in bit lines of a memory device | Eric Kwesi Donkoh | 2011-05-31 |
| 7656702 | Ultra low voltage, low leakage, high density, variation tolerant memory bit cells | Matthew W. Ernest, Brian A. Kuns | 2010-02-02 |
| 7516173 | Carry-skip adder having merged carry-skip cells with sum cells | — | 2009-04-07 |
| 7509368 | Sparse tree adder circuit | Mark A. Anders, Sanu K. Mathew, Nanda Siddaiah | 2009-03-24 |
| 7325024 | Adder circuit with sense-amplifier multiplexer front-end | Sanu K. Mathew, Mark A. Anders, Ram Krishnamurthy | 2008-01-29 |
| 7202703 | Single stage level restore circuit with hold functionality | — | 2007-04-10 |
| 7161389 | Ratioed logic circuits with contention interrupt | Daniel J. Deleganes | 2007-01-09 |
| 7002855 | Leakage tolerant register file | Pankaj Aswal, Mohammad M. Haq, Marijan Persun | 2006-02-21 |
| 6958629 | Single stage, level restore circuit with mixed signal inputs | — | 2005-10-25 |
| 6922082 | Select logic for low voltage swing circuits | — | 2005-07-26 |
| 6836755 | Method and apparatus for fully automated signal integrity analysis for domino circuitry | Mark Nardin, Hans J. Greub | 2004-12-28 |