Mel Bazes has been granted 50 US patents while listed as an inventor at Intel . The first was granted in 1985 and the most recent in August 2014. Mel Bazes ranks #53,743 of 4,157,543 US inventors in our database (top 1.3%). Patent records list Mel Bazes in Haifa, CA, IL.
Patents per Year Patents granted per year, 1985 to 2014 Bar chart with a peak of 5 patents in 1990. peak 5 1985: 2 patents 1985 1987: 1 patents 1989: 1 patents 1990: 5 patents 1990 1991: 2 patents 1992: 2 patents 1994: 1 patents 1994 1995: 2 patents 1996: 3 patents 1997: 2 patents 1997 1998: 2 patents 1999: 2 patents 2000: 1 patents 2000 2001: 1 patents 2002: 1 patents 2003: 2 patents 2003 2005: 1 patents 2006: 2 patents 2007: 1 patents 2007 2008: 1 patents 2009: 2 patents 2010: 5 patents 2010 2011: 3 patents 2013: 2 patents 2014: 3 patents 2014
Issued Patents All Time
Profile Widget
Showing 1–25 of 50 patents
Patent # Title Co-Inventors Date Approx Value ⓘ
8810320
Phase-locked loop runaway detector
—
2014-08-19
$1,468,000
8729942
Race free semi-dynamic D-type flip flop
—
2014-05-20
$1,682,000
8624646
Method and apparatus for generating asymmetrically deskewed complementary signals
—
2014-01-07
$1,597,000
8593193
Complementary semi-dynamic D-type flip-flop
—
2013-11-26
$2,091,000
8593194
Race free semi-dynamic D-type flip-flop
—
2013-11-26
$2,091,000
8044692
Level-restorer for supply-regulated PLL
—
2011-10-25
8030975
Method and apparatus for generating frequency divided signals
—
2011-10-04
$2,700,000
7888990
Phase locked loop charge pump reference current bootstrapping
—
2011-02-15
$7,938,000
7843247
Method and apparatus for controlled voltage level shifting
—
2010-11-30
$20,670,000
7839220
Phase-locked loop runaway detector
—
2010-11-23
$4,551,000
7804341
Level-restored for supply-regulated PLL
—
2010-09-28
$9,955,000
7800417
Method and apparatus for generating frequency divided signals
—
2010-09-21
$7,551,000
7791379
High-speed reduced-output-swing self-biased fully-complementary CMOS comparator with rail-to-rail input common-mode range
—
2010-09-07
$8,239,000
7598777
High-speed reduced-output-swing self-biased fully-complementary CMOS comparator with rail-to-rail input common-mode range
—
2009-10-06
$12,351,000
7557625
Phase locked loop charge pump reference current bootstrapping
—
2009-07-07
$13,514,000
7375575
Method and apparatus for controlled voltage level shifting
—
2008-05-20
$22,559,000
7236518
Deskewing differential repeater
—
2007-06-26
$20,503,000
7123066
Speed-locked loop to provide speed information based on die operating conditions
—
2006-10-17
$12,433,000
6982580
Speed-locked loop to provide speed information based on die operating conditions
—
2006-01-03
$22,757,000
6856172
Sequential logic circuit for frequency division
—
2005-02-15
$22,930,000
6633186
Speed-locked loop to provide speed information based on die operating conditions
—
2003-10-14
$51,971,000
6617911
Reducing output capacitance of digital-to-time domain converter for very high frequency digital waveform synthesis
—
2003-09-09
$39,870,000
6469579
Boosted high gain, very wide common mode range, self-biased operational amplifier
—
2002-10-22
$55,590,000
6278323
High gain, very wide common mode range, self-biased operational amplifier
—
2001-08-21
$236,055,000
6140857
Method and apparatus for reducing baseline wander
—
2000-10-31
$377,936,000