Issued Patents All Time
Showing 226–250 of 263 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7587614 | Encryption algorithm optimized for FPGAs | — | 2009-09-08 |
| 7565388 | Logic cell supporting addition of three binary words | Gregg William Baeckler, James Schleicher, Richard Yuan | 2009-07-21 |
| 7484081 | Method and apparatus for protecting designs in SRAM-based programmable logic devices | Gregory Steinke, Guy Schlacter, Bernd Neidermeier | 2009-01-27 |
| 7467176 | Saturation and rounding in multiply-accumulate blocks | Leon Zheng, Steven Perry, Paul Metzgen, Nitin Prasad, William Hwang | 2008-12-16 |
| 7437401 | Multiplier-accumulator block mode splitting | Leon Zheng, Steven Perry, Paul Metzgen, Gregory Starr, William Hwang +1 more | 2008-10-14 |
| 7346644 | Devices and methods with programmable logic and digital signal processing regions | Gregory Starr, Chiao Kai Hwang | 2008-03-18 |
| 7302460 | Arrangement of 3-input LUT's to implement 4:2 compressors for multiple operand arithmetic | — | 2007-11-27 |
| 7287051 | Multi-functional digital signal processing circuitry | — | 2007-10-23 |
| 7260154 | Method and apparatus for implementing a multiple constraint length Viterbi decoder | Volker Mauer, Alejandro Diaz-Manero | 2007-08-21 |
| 7256715 | Data compression using dummy codes | — | 2007-08-14 |
| 7230451 | Programmable logic device with routing channels | — | 2007-06-12 |
| 7228531 | Methods and apparatus for optimizing a processor core on a programmable chip | — | 2007-06-05 |
| 7216139 | Programmable logic device including multipliers and configurations thereof to reduce resource utilization | Chiao Kai Hwang, Gregory Starr | 2007-05-08 |
| 7173985 | Method and apparatus for implementing a Viterbi decoder | Alejandro Diaz-Manero, Robert Cottrell | 2007-02-06 |
| 7142010 | Programmable logic device including multipliers and configurations thereof to reduce resource utilization | Chiao Kai Hwang, Gregory Starr | 2006-11-28 |
| 7142011 | Programmable logic device with routing channels | — | 2006-11-28 |
| 7119576 | Devices and methods with programmable logic and digital signal processing regions | Gregory Starr, Chiao Kai Hwang | 2006-10-10 |
| 7109895 | High performance Lempel Ziv compression architecture | — | 2006-09-19 |
| 7109753 | Programmable logic device with routing channels | — | 2006-09-19 |
| 7084664 | Integrated circuits with reduced interconnect overhead | Kwan Yee Martin Lee, Ali Burney | 2006-08-01 |
| 7035356 | Efficient method for traceback decoding of trellis (Viterbi) codes | — | 2006-04-25 |
| 7024446 | Circuitry for arithmetically accumulating a succession of arithmetic values | Nitin Prasad | 2006-04-04 |
| 7003544 | Method and apparatus for generating a squared value for a signed binary number | — | 2006-02-21 |
| 6987401 | Compare, select, sort, and median-filter apparatus in programmable logic devices and associated methods | Jonah Graham | 2006-01-17 |
| 6978287 | DSP processor architecture with write datapath word conditioning and analysis | — | 2005-12-20 |