Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5661731 | Method for shrinking a clock cycle when testing high speed microprocessor designs | Marc E. Wegman | 1997-08-26 |
| 5608741 | Fast parity generator using complement pass-transistor logic | Sudarshan Kumar, Shyue L. Kuo | 1997-03-04 |