Issued Patents All Time
Showing 26–50 of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6785188 | Fully synchronous pipelined RAM | — | 2004-08-31 |
| 6665202 | Content addressable memory (CAM) devices that can identify highest priority matches in non-sectored CAM arrays and methods of operating same | Craig Lindahl, Yong Zhao | 2003-12-16 |
| 6591354 | Separate byte control on fully synchronous pipelined SRAM | Mark Baumann | 2003-07-08 |
| 6577520 | Content addressable memory with programmable priority weighting and low cost match detection | — | 2003-06-10 |
| 6567338 | Fully synchronous pipelined RAM | — | 2003-05-20 |
| 6470418 | Pipelining a content addressable memory cell array for low-power operation | Chuen-Der Lien, Chau-Chin Wu | 2002-10-22 |
| 6370613 | Content addressable memory with longest match detect | Thomas Diede | 2002-04-09 |
| 6249480 | Fully synchronous pipelined ram | — | 2001-06-19 |
| 6212607 | Multi-ported memory architecture using single-ported RAM | Michael J. Miller, Jeff Smith, Mark Baumann, Chris Schott | 2001-04-03 |
| 6115320 | Separate byte control on fully synchronous pipelined SRAM | Mark Baumann | 2000-09-05 |
| 6108756 | Semaphore enhancement to allow bank selection of a shared resource memory device | Michael J. Miller, Jeff Smith, Mark Baumann | 2000-08-22 |
| 6094399 | Fully synchronous pipelined RAM | — | 2000-07-25 |
| 6081478 | Separate byte control on fully synchronous pipelined SRAM | Mark Baumann | 2000-06-27 |
| 5950233 | Interleaved burst address counter with reduced delay between rising clock edge and burst address transfer to memory | Raymond M. Chu, David J. Pilling | 1999-09-07 |
| 5920580 | Multiple error detection in error detection correction circuits | — | 1999-07-06 |
| 5875151 | Fully synchronous pipelined ram | — | 1999-02-23 |
| 5841732 | Fully synchronous pipelined ram | — | 1998-11-24 |
| 5838631 | Fully synchronous pipelined ram | — | 1998-11-17 |
| 5828606 | Fully synchronous pipelined RAM | — | 1998-10-27 |
| 5807136 | Space saving connector layout | — | 1998-09-15 |
| 5751638 | Mail-box design for non-blocking communication across ports of a multi-port device | Michael J. Miller, Jeff Smith, Mark Baumann | 1998-05-12 |
| 5581564 | Diagnostic circuit | Michael J. Miller | 1996-12-03 |
| 5331645 | Expandable digital error detection and correction device | Michael J. Miller, Andy Peng-Pui Chan, Robert W. Stodieck | 1994-07-19 |
| 5175819 | Cascadable parallel to serial converter using tap shift registers and data shift registers while receiving input data from FIFO buffer | Danh Le Ngoc, Fulam Au | 1992-12-29 |
| 4931974 | Sixteen-bit programmable pipelined arithmetic logic unit | Danh Le Ngoc | 1990-06-05 |