Issued Patents All Time
Showing 51–75 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6466152 | Resistor cascade for forming electrical reference quantities and analog/digital converter | Wolfgang Hoenlein | 2002-10-15 |
| 6462979 | Integrated memory having memory cells with magnetoresistive storage effect | Till Schlosser | 2002-10-08 |
| 6366494 | Magnetoresistive memory having elevated interference immunity | Werner Weber, Gunther Plasa | 2002-04-02 |
| 6181183 | Steep edge time-delay relay | Paul-Werner von Basse, Michael Bollu, Doris Schmitt-Landsiedel | 2001-01-30 |
| 6166565 | Circuit for comparing two electrical quantities | Stefan Prange, Erdmute Wohlrab, Werner Weber | 2000-12-26 |
| 6160729 | Associative memory and method for the operation thereof | Stefan Jung, Werner Weber, Andreas Luck, by Manfred Luck, heir, by Inge Booken, heir | 2000-12-12 |
| 6138227 | Device for the jump-like addressing of specific lines of a serially operating digital memory | Doris Schmitt-Landsiedel, Paul-Werner von Basse, Michael Bollu | 2000-10-24 |
| 6097661 | Pointer circuit with low surface requirement high speed and low power loss | Doris Schmitt-Landsiedel, Paul-Werner von Basse, Michael Bollu, Ute Kollmer, Andreas Luck +2 more | 2000-08-01 |
| 6078190 | Threshold logic with improved signal-to-noise ratio | Werner Weber, Andreas Luck | 2000-06-20 |
| 6044006 | Method for programming a ROM cell arrangement | Paul-Werner von Basse, Doris Schmitt-Lansiedel, Michael Bollu | 2000-03-28 |
| 6037885 | Digital/analog converter using a floating gate MOS neuron transistor with capacitive coupling | Doris Schmitt-Landsiedel, Doktorand Andreas Luck, Werner Weber | 2000-03-14 |
| 6037626 | Semiconductor neuron with variable input weights | Werner Weber | 2000-03-14 |
| 6028803 | Read amplifier for semiconductor memory cells with means to compensate threshold voltage differences in read amplifier transistors | Thomas Edward Kopley, Werner Weber | 2000-02-22 |
| 5991789 | Circuit arrangement for realizing logic elements that can be represented by threshold value equations | Stefan Prange, Erdmute Wohlrab, Werner Weber | 1999-11-23 |
| 5990709 | Circuit for comparing two electrical quantities provided by a first neuron MOS field effect transistor and a reference source | Stefan Prange, Erdmute Wohlrab, Werner Weber | 1999-11-23 |
| 5986464 | Threshold logic circuit with low space requirement | Andreas Luck, Werner Weber | 1999-11-16 |
| 5942912 | Devices for the self-adjusting setting of the operating point in amplifier circuits with neuron MOS transistors | Werner Weber, Andreas Luck, Doris Schmitt-Landsiedel | 1999-08-24 |
| 5939945 | Amplifier with neuron MOS transistors | Werner Weber, Andreas Luck, Erdmute Wohlrab, Doris Schmitt-Landsiedel | 1999-08-17 |
| 5831892 | Matrix memory in virtual ground architecture | Paul-Werner von Basse, Michael Bollu, Doris Schmitt-Landsiedel | 1998-11-03 |
| 5825686 | Multi-value read-only memory cell having an improved signal-to-noise ratio | Doris Schmitt-Landsiedel, Michael Bollu, Paul-Werner von Basse | 1998-10-20 |
| 5825701 | Memory cell arrangement of memory cells arranged in the form of a matrix | Paul-Werner von Basse, Doris Schmitt-Landsiedel, Michael Bollu | 1998-10-20 |
| 5818112 | Arrangement for capacitive signal transmission between the chip layers of a vertically integrated circuit | Werner Weber, Stefan Kuehn, Michael Kleiner | 1998-10-06 |
| 5751742 | Serially accessible memory means with high error correctability | Paul-Werner von Basse, Michael Bollu, Doris Schmitt-Landsiedel | 1998-05-12 |
| 5732013 | Matrix memory (virtual ground) | Paul-Werner von Basse, Doris Schmitt-Landsiedel, Michael Bollu | 1998-03-24 |
| 5701037 | Arrangement for inductive signal transmission between the chip layers of a vertically integrated circuit | Werner Weber, Stefan Kuehn, Michael Kleiner | 1997-12-23 |