Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12271259 | Out-of-bounds recovery circuit | Ashish Darbari | 2025-04-08 |
| 12175179 | Assessing performance of a hardware design using formal evaluation logic | Ashish Darbari | 2024-12-24 |
| 12093621 | Detecting out-of-bounds violations in a hardware design using formal verification | Ashish Darbari | 2024-09-17 |
| 12050849 | Livelock detection in a hardware design using formal evaluation logic | Ashish Darbari | 2024-07-30 |
| 11948652 | Formal verification tool to verify hardware design of memory unit | Ashish Darbari | 2024-04-02 |
| 11847456 | Livelock recovery circuit for detecting illegal repetition of an instruction and transitioning to a known state | Ashish Darbari | 2023-12-19 |
| 11663386 | Detecting out-of-bounds violations in a hardware design using formal verification | Ashish Darbari | 2023-05-30 |
| 11593193 | Out-of-bounds recovery circuit | Ashish Darbari | 2023-02-28 |
| 11531799 | Assessing performance of a hardware design using formal evaluation logic | Ashish Darbari | 2022-12-20 |
| 11467840 | Livelock recovery circuit for detecting illegal repetition of an instruction and transitioning to a known state | Ashish Darbari | 2022-10-11 |
| 11373025 | Livelock detection in a hardware design using formal evaluation logic | Ashish Darbari | 2022-06-28 |
| 11250927 | Formal verification tool to verify hardware design of memory unit | Ashish Darbari | 2022-02-15 |
| 11250192 | Detecting out-of-bounds violations in a hardware design using formal verification | Ashish Darbari | 2022-02-15 |
| 11030039 | Out-of-bounds recovery circuit | Ashish Darbari | 2021-06-08 |
| 10963611 | Assessing performance of a hardware design using formal evaluation logic | Ashish Darbari | 2021-03-30 |
| 10936775 | Detecting out-of-bounds violations in a hardware design using formal verification | Ashish Darbari | 2021-03-02 |
| 10909289 | Livelock detection in a hardware design using formal evaluation logic | Ashish Darbari | 2021-02-02 |
| 10817367 | Out-of-bounds recovery circuit | Ashish Darbari | 2020-10-27 |
| 10755011 | Detecting out-of-bounds violations in a hardware design using formal verification | Ashish Darbari | 2020-08-25 |
| 10580511 | Hardware monitor to verify memory units | Ashish Darbari | 2020-03-03 |
| 10552155 | Livelock recovery circuit configured to detect illegal repetition of an instruction and transition to a known state | Ashish Darbari | 2020-02-04 |
| 10359825 | Dynamic power measurement using formal | John Alexander Osborne Netterville, Ashish Darbari | 2019-07-23 |
| 10346571 | Livelock detection in a hardware design using formal evaluation logic | Ashish Darbari | 2019-07-09 |
| 10331831 | Assessing performance of a hardware design using formal evaluation logic | Ashish Darbari | 2019-06-25 |
| 10210119 | Arbiter verification | Ashish Darbari, John Alexander Osborne Netterville | 2019-02-19 |