Issued Patents All Time
Showing 26–50 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8756456 | Control and monitoring for fast millimeter-wave link using out-of-band wireless channel | Nobuyuki Ohba, Kohji Takano | 2014-06-17 |
| 8644667 | Backplane structure allowing setting of equal peer-to-peer communication distance between two blades arbitrarily inserted into a plurality of fixedly arranged slots | Seiji Munetoh, Atsuya Okazaki | 2014-02-04 |
| 8578239 | Calculation technique for sum-product decoding method (belief propagation method) based on scaling of input log-likelihood ratio by noise variance | Toshiyuki Yamane | 2013-11-05 |
| 8514987 | Compensation for data deviation caused by frequency offset using timing correlation value | Daiju Nakano | 2013-08-20 |
| 8442028 | Packet communication system, communication method and program | Yasushi Negishi, Atsuya Okazaki | 2013-05-14 |
| 8391815 | Radio receiver, radio communication system, radio communication method, and program | Daiju Nakano | 2013-03-05 |
| 8379708 | Method and circuit for digitally filtering a signal | Daiju Nakano, Kohji Takano | 2013-02-19 |
| 8346080 | Optical network system and memory access method | Atsuya Okazaki | 2013-01-01 |
| 8289087 | Method for detecting and correcting phase shift between I data clock in Q data clock in quadrature modulator or quadrature demodulator | Yasuteru Kohda, Nobuyuki Ohba | 2012-10-16 |
| 8233622 | Transmitting parallel data via high-speed serial interconnection | Atsuya Okazaki | 2012-07-31 |
| 8037395 | Encoding and decoding method for packet recovery | Daiju Nakano | 2011-10-11 |
| 8005161 | Method, hardware product, and computer program product for performing high data rate wireless transmission | Daiju Nakano | 2011-08-23 |
| 7956348 | Complementary logic circuit | — | 2011-06-07 |
| 7534710 | Coupled quantum well devices (CQWD) containing two or more direct selective contacts and methods of making same | Dennis M. Newns, Chang C. Tsuei | 2009-05-19 |
| 7296209 | Apparatus for encoding and decoding | Toshiyuki Yamane | 2007-11-13 |
| 7185258 | Signal processing method, signal processing system, program for signal processing, and computer-readable storage medium on which this program is recorded | Sumio Morioka, Toshiyuki Yamane | 2007-02-27 |
| 7010738 | Combinational circuit, and encoder, decoder and semiconductor device using this combinational circuit | Sumio Morioka, Toshiyuki Yamane | 2006-03-07 |
| 6928601 | Decoding circuit, and decoder, decoding method and semiconductor device that use the decoding circuit | Sumio Morioka, Toshiyuki Yamane | 2005-08-09 |
| 6912558 | MULTIPLICATION MODULE, MULTIPLICATIVE INVERSE ARITHMETIC CIRCUIT, MULTIPLICATIVE INVERSE ARITHMETIC CONTROL METHOD, APPARATUS EMPLOYING MULTIPLICATIVE INVERSE ARITHMETIC CIRCUIT, AND CRYPTOGRAPHIC APPARATUS AND ERROR CORRECTION DECODER THEREFOR | Sumio Morioka | 2005-06-28 |
| 6721919 | Shared encoder used in error correction having multiple encoders of different maximum error correction capabilities | Sumio Morioka | 2004-04-13 |
| 6487691 | Reed-solomon decoder | Sumio Morioka | 2002-11-26 |
| 6199139 | Refresh period control apparatus and method, and computer | Shigenori Shimizu | 2001-03-06 |
| 5926839 | Method and apparatus of burst read and pipelined dynamic random access memory having multiple pipelined stages with DRAM controller and buffers integrated on a single chip | — | 1999-07-20 |
| 5901304 | Emulating quasi-synchronous DRAM with asynchronous DRAM | Wei Hwang, Rajiv V. Joshi | 1999-05-04 |
| 5883814 | System-on-chip layout compilation | Wing K. Luk, Wei Hwang | 1999-03-16 |