Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6338134 | Method and system in a superscalar data processing system for the efficient processing of an instruction by moving only pointers to data | Frank C. Harwood | 2002-01-08 |
| 6260118 | Snooping a variable number of cache addresses in a multiple processor system by a single snoop request | Thomas B. Genduso | 2001-07-10 |
| 6151661 | Cache memory storage space management system and method | Henry Walton Adams, III, Thomas B. Genduso | 2000-11-21 |
| 6009509 | Method and system for the temporary designation and utilization of a plurality of physical registers as a stack | Thomas B. Genduso | 1999-12-28 |
| 6003126 | Special instruction register including allocation field utilized for temporary designation of physical registers as general registers | Dieu Dai Huynh | 1999-12-14 |
| 5923898 | System for executing I/O request when an I/O request queue entry matches a snoop table entry or executing snoop when not matched | Thomas B. Genduso | 1999-07-13 |
| 5900017 | Snooping a variable number of cache addresses in a multiple processor system by a single snoop request | Thomas B. Genduso | 1999-05-04 |
| 5893148 | System and method for allocating cache memory storage space | Thomas B. Genduso | 1999-04-06 |
| 5664150 | Computer system with a device for selectively blocking writebacks of data from a writeback cache to memory | Gerald G. Isaac, John K. Langgood, Kimberly K. Sendlein, John Joseph Szarek, Edward M. Yee | 1997-09-02 |
| 5598542 | Method and apparatus for bus arbitration in a multiple bus information handling system using time slot assignment values | — | 1997-01-28 |
| 5293491 | Data processing system and memory controller for lock semaphore operations | Richard Allen Kelley, Leslie F. McDermott | 1994-03-08 |
| 5003465 | Method and apparatus for increasing system throughput via an input/output bus and enhancing address capability of a computer system during DMA read/write operations between a common memory and an input/output device | Douglas R. Chisholm, Robert G. Iseminger, Richard Allen Kelley, James T. Moyer, Mark C. Snedaker | 1991-03-26 |
| 4695950 | Fast two-level dynamic address translation method and means | Henry R. Brandt, Patrick M. Gannon, Timothy R. Marchini | 1987-09-22 |