Issued Patents All Time
Showing 51–75 of 86 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7660942 | Daisy chainable self timed memory chip | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2010-02-09 |
| 7660940 | Carrier having daisy chain of self timed memory chips | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2010-02-09 |
| 7650455 | Spider web interconnect topology utilizing multiple port connection | Gerald K. Bartley, Darryl J. Becker, John Michael Borkenhagen, Paul Eric Dahlen, William Paul Hovis +1 more | 2010-01-19 |
| 7627711 | Memory controller for daisy chained memory chips | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2009-12-01 |
| 7620763 | Memory chip having an apportionable data bus | Gerald K. Bartley, Darryl J. Becker, John Michael Borkenhagen, Paul Eric Dahlen, Andrew Benson Maki +1 more | 2009-11-17 |
| 7617350 | Carrier having daisy chained memory chips | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2009-11-10 |
| 7577811 | Memory controller for daisy chained self timed memory chips | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2009-08-18 |
| 7553696 | Method for implementing component placement suspended within grid array packages for enhanced electrical performance | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2009-06-30 |
| 7546410 | Self timed memory chip having an apportionable data bus | Gerald K. Bartley, Darryl J. Becker, John Michael Borkenhagen, Paul Eric Dahlen, Andrew Benson Maki +1 more | 2009-06-09 |
| 7545664 | Memory system having self timed daisy chained memory chips | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2009-06-09 |
| 7496711 | Multi-level memory architecture with data prioritization | Gerald K. Bartley, John Michael Borkenhagen, William Paul Hovis | 2009-02-24 |
| 7492662 | Structure and method of implementing power savings during addressing of DRAM architectures | Gerald K. Bartley, Darryl J. Becker, John Michael Borkenhagen, William Paul Hovis | 2009-02-17 |
| 7490186 | Memory system having an apportionable data bus and daisy chained memory chips | Gerald K. Bartley, Darryl J. Becker, John Michael Borkenhagen, Paul Eric Dahlen, Andrew Benson Maki +1 more | 2009-02-10 |
| 7480201 | Daisy chainable memory chip | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2009-01-20 |
| 7477568 | Using common mode differential data signals of DDR2 SDRAM for control signal transmission | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2009-01-13 |
| 7472360 | Method for implementing enhanced wiring capability for electronic laminate packages | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson +1 more | 2008-12-30 |
| 7472368 | Method for implementing vertically coupled noise control through a mesh plane in an electronic package design | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2008-12-30 |
| 7402912 | Method and power control structure for managing plurality of voltage islands | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2008-07-22 |
| 7362651 | Using common mode differential data signals of DDR2 SDRAM for control signal transmission | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2008-04-22 |
| 7345900 | Daisy chained memory system | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2008-03-18 |
| 7345901 | Computer system having daisy chained self timed memory chips | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2008-03-18 |
| 7342816 | Daisy chainable memory chip | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2008-03-11 |
| 7326857 | Method and structure for creating printed circuit boards with stepped thickness | Mark J. Jeanson | 2008-02-05 |
| 7317401 | Method and mechanical tamper-evident case fastener | Mark J. Jeanson | 2008-01-08 |
| 7202685 | Embedded probe-enabling socket with integral probe structures | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2007-04-10 |