Issued Patents All Time
Showing 26–50 of 86 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8037258 | Structure for dual-mode memory chip for high capacity memory subsystem | Gerald K. Bartley, John Michael Borkenhagen | 2011-10-11 |
| 8037270 | Structure for memory chip for high capacity memory subsystem supporting replication of command data | Gerald K. Bartley, John Michael Borkenhagen | 2011-10-11 |
| 8019949 | High capacity memory subsystem architecture storing interleaved data for reduced bus speed | Gerald K. Bartley, John Michael Borkenhagen | 2011-09-13 |
| 7996641 | Structure for hub for supporting high capacity memory subsystem | Gerald K. Bartley, John Michael Borkenhagen | 2011-08-09 |
| 7952478 | Capacitance-based microchip exploitation detection | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2011-05-31 |
| 7954081 | Implementing enhanced wiring capability for electronic laminate packages | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson +1 more | 2011-05-31 |
| 7945883 | Apparatus, and computer program for implementing vertically coupled noise control through a mesh plane in an electronic package design | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2011-05-17 |
| 7921264 | Dual-mode memory chip for high capacity memory subsystem | Gerald K. Bartley, John Michael Borkenhagen | 2011-04-05 |
| 7921271 | Hub for supporting high capacity memory subsystem | Gerald K. Bartley, John Michael Borkenhagen | 2011-04-05 |
| 7884625 | Capacitance structures for defeating microchip tampering | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2011-02-08 |
| 7882479 | Method and apparatus for implementing redundant memory access using multiple controllers on the same bank of memory | Gerald K. Bartley, Darryl J. Becker, John Michael Borkenhagen, Paul Eric Dahlen, William Paul Hovis | 2011-02-01 |
| 7852103 | Implementing at-speed Wafer Final Test (WFT) with complete chip coverage | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson +1 more | 2010-12-14 |
| 7844769 | Computer system having an apportionable data bus and daisy chained memory chips | Gerald K. Bartley, Darryl J. Becker, John Michael Borkenhagen, Paul Eric Dahlen, Andrew Benson Maki +1 more | 2010-11-30 |
| 7838336 | Method and structure for dispensing chip underfill through an opening in the chip | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2010-11-23 |
| 7822936 | Memory chip for high capacity memory subsystem supporting replication of command data | Gerald K. Bartley, John Michael Borkenhagen | 2010-10-26 |
| 7818512 | High capacity memory subsystem architecture employing hierarchical tree configuration of memory modules | Gerald K. Bartley, John Michael Borkenhagen | 2010-10-19 |
| 7810065 | System and method for implementing optimized creation of openings for de-gassing in an electronic package | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson +1 more | 2010-10-05 |
| 7809913 | Memory chip for high capacity memory subsystem supporting multiple speed bus | Gerald K. Bartley, John Michael Borkenhagen | 2010-10-05 |
| 7791978 | Design structure of implementing power savings during addressing of DRAM architectures | Gerald K. Bartley, Darryl J. Becker, John Michael Borkenhagen, William Paul Hovis | 2010-09-07 |
| 7725762 | Implementing redundant memory access using multiple controllers on the same bank of memory | Gerald K. Bartley, Darryl J. Becker, John Michael Borkenhagen, Paul Eric Dahlen, William Paul Hovis | 2010-05-25 |
| 7707379 | Dynamic latency map for memory optimization | Gerald K. Bartley, John Michael Borkenhagen, William Paul Hovis | 2010-04-27 |
| 7701244 | False connection for defeating microchip exploitation | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson +1 more | 2010-04-20 |
| 7675164 | Method and structure for connecting, stacking, and cooling chips on a flexible carrier | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2010-03-09 |
| 7673093 | Computer system having daisy chained memory chips | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2010-03-02 |
| 7667487 | Techniques for providing switchable decoupling capacitors for an integrated circuit | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Andrew Benson Maki, Mark O. Maxson | 2010-02-23 |