Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5652853 | Multi-zone relocation facility computer memory system | Karl J. Duvalsaint, Moon J. Kim, Barry W. Krumm, Donald W. McCauley, John F. Scanlon | 1997-07-29 |
| 5461721 | System for transferring data between I/O devices and main or expanded storage under dynamic control of independent indirect address words (IDAWs) | Roger L. Cormier, Robert J. Dugan, Kenneth J. Fredericks, Moon J. Kim, Allen H. Preston +3 more | 1995-10-24 |
| 5426748 | Guest/host extended addressing method and means with contiguous access list entries | James G. Brenza, Joseph M. Gdaniec, Kathryn Marie Jackson, Mark M. Maccabee, Casper A. Scalzi +1 more | 1995-06-20 |
| 5404563 | Scheduling normally interchangeable facilities in multiprocessor computer systems | Lucina L. Green, Roger E. Hough, Sandra L. Rankin, Stephen J. Schmandt, Ronald M. Smith, Sr. +3 more | 1995-04-04 |
| 5381535 | Data processing control of second-level quest virtual machines without host intervention | Roger E. Hough, Robert E. Murray | 1995-01-10 |
| 5317705 | Apparatus and method for TLB purge reduction in a multi-level machine system | Patrick M. Gannon, Roger E. Hough, Robert E. Murray | 1994-05-31 |
| 5222215 | CPU expansive gradation of I/O interruption subclass recognition | Norman C. Chou, Roger E. Hough, Moon J. Kim, James C. Mazurowski, Donald W. McCauley +3 more | 1993-06-22 |
| 4843541 | Logical resource partitioning of a data processing system | George H. Bean, Terry L. Borden, Mark S. Farrell, Roger E. Hough, Francis E. Johnson +6 more | 1989-06-27 |
| 4779188 | Selective guest system purge control | Roger E. Hough, Peter H. Tallman, Thomas O. Curlee, III | 1988-10-18 |
| 4598364 | Efficient trace method adaptable to multiprocessors | Arthur L. Levin, Ronald M. Smith, John H. Wilson | 1986-07-01 |
| 4494189 | Method and means for switching system control of CPUs | George H. Bean | 1985-01-15 |
| 4456954 | Virtual machine system with guest architecture emulation using hardware TLB's for plural level address translations | Robert J. Bullions, III, Thomas O. Curlee, III, Bruce L. McGilvray, Ethel L. Richardson | 1984-06-26 |