Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9298630 | Optimizing memory bandwidth consumption using data splitting with software caching | Christopher M. Barton, Shimin Cui, Satish K. Sadasivam, Raul E. Silvera, Steven Wayne White | 2016-03-29 |
| 9229746 | Identifying load-hit-store conflicts | Venkat R. Indukuru, Alexander Erik Mericas, Satish K. Sadasivam | 2016-01-05 |
| 9229745 | Identifying load-hit-store conflicts | Venkat R. Indukuru, Alexander Erik Mericas, Satish K. Sadasivam | 2016-01-05 |
| 9032375 | Performance bottleneck identification tool | Prathiba Kumar, Rajan Ravindran, Satish K. Sadasivam | 2015-05-12 |
| 8745607 | Reducing branch misprediction impact in nested loop code | Steven Wayne White | 2014-06-03 |
| 8245084 | Two-level representative workload phase detection | Robert H. Bell, Jr., Wen-Tzer T. Chen, Venkat R. Indukuru, Pattabi M. Seshadri | 2012-08-14 |
| 8091073 | Scaling instruction intervals to identify collection points for representative instruction traces | Robert H. Bell, Jr., Wen-Tzer T. Chen, Richard J. Eickemeyer, Venkat R. Indukuru, Pattabi M. Seshadri | 2012-01-03 |
| 8010334 | Method and apparatus for evaluating integrated circuit design performance using basic block vectors, cycles per instruction (CPI) information and microarchitecture dependent information | Robert H. Bell, Jr., Thomas W. Chen, Venkat R. Indukuru, Alex E. Mericas, Pattabi M. Seshadri | 2011-08-30 |
| 7904870 | Method and apparatus for integrated circuit design model performance evaluation using basic block vector clustering and fly-by vector clustering | Robert H. Bell, Jr., Wen-Tzer T. Chen, Venkat R. Indukuru, Pattabi M. Seshadri | 2011-03-08 |
| 7844928 | Method and apparatus for evaluating integrated circuit design performance using enhanced basic block vectors that include data dependent information | Robert H. Bell, Jr., Thomas W. Chen, Richard J. Eickemeyer, Venkat R. Indukuru, Pattabi M. Seshadri | 2010-11-30 |
| 7770140 | Method and apparatus for evaluating integrated circuit design model performance using basic block vectors and fly-by vectors including microarchitecture dependent information | Robert H. Bell, Jr., Thomas W. Chen, Venkat R. Indukuru, Pattabi M. Seshadri | 2010-08-03 |