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Hyperprocessor |
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2009-05-12 |
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System independent and scalable packet buffer management architecture for network processors |
Ramesh Chandra, Bernd Stramm |
2008-12-23 |
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Octagonal interconnection network for linking processing nodes on an SOC device and method of operating same |
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2007-05-15 |
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Fetch branch architecture for reducing branch penalty without branch prediction |
Ramesh Chandra |
2006-03-07 |
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Method and device for computing the number of bits set to one in an arbitrary length word |
Alain Mellan |
2004-09-21 |
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Method and device for computing incremental checksums |
Kartik V. Talsania, Vincent E. Wass |
2003-11-04 |
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Floating point pipeline with a leading zeros anticipator circuit |
Michael Thomas Dibrino |
2003-04-01 |
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Method and apparatus for generating an end-around carry in a floating-point pipeline within a computer system |
Michael Thomas Dibrino |
2000-05-09 |
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Super scalar computer architecture using remand and recycled general purpose register to manage out-of-order execution of instructions |
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1996-01-02 |
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Method and apparatus for floating point normalization |
Christopher H. Olson |
1995-01-24 |
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Floating point arithmetic unit with size efficient pipelined multiply-add architecture |
Tan V. Chu, Christopher H. Olson |
1993-08-31 |
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Circuit and method for performing integer power operations |
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1993-03-16 |
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System for multiple error detection with single and double bit error correction |
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1986-05-13 |
