Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8341428 | System and method to protect computing systems | Mariette Awad, Adam E. Trojanowski, Sebastian T. Ventrone | 2012-12-25 |
| 7962322 | Design structure for compensating for variances of a buried resistor in an integrated circuit | Mariette Awad, Kai D. Feng | 2011-06-14 |
| 7886237 | Method of generating a functional design structure | Mariette Awad, Kai D. Feng | 2011-02-08 |
| 7834444 | Heatplates for heatsink attachment for semiconductor chips | John J. Maloney | 2010-11-16 |
| 7666712 | Design of BEOL patterns to reduce the stresses on structures below chip bondpads | Mariette Awad, Kai D. Feng | 2010-02-23 |
| 7595681 | Method and apparatus for compensating for variances of a buried resistor in an integrated circuit | Mariette Awad, Kai D. Feng | 2009-09-29 |
| 7498673 | Heatplates for heatsink attachment for semiconductor chips | John J. Maloney | 2009-03-03 |
| 7489038 | Design of BEOL patterns to reduce the stresses on structures below chip bondpads | Mariette Awad, Kai D. Feng | 2009-02-10 |
| 7251872 | Method for forming a chip package | Paul Panaccione | 2007-08-07 |
| 7071559 | Design of beol patterns to reduce the stresses on structures below chip bondpads | Mariette Awad, Kai D. Feng | 2006-07-04 |
| 6894382 | Optimized electronic package | John J. Maloney | 2005-05-17 |
| 6815806 | Asymmetric partially-etched leads for finer pitch semiconductor chip package | Paul Panaccione | 2004-11-09 |