Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10830818 | Ensuring completeness of interface signal checking in functional verification | Minh Cuong Tran, Gerrit Koch, Joerg Walter | 2020-11-10 |
| 10823782 | Ensuring completeness of interface signal checking in functional verification | Minh Cuong Tran, Gerrit Koch, Joerg Walter | 2020-11-03 |
| 10764166 | Injecting lost packets and protocol errors in a simulation environment | Dirk Allmendinger, Roopesh A. Matayambath, Juergen Ruf | 2020-09-01 |
| 10678974 | System and method for generation of an integrated circuit design | Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann | 2020-06-09 |
| 10572617 | System and method for generation of an integrated circuit design | Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann | 2020-02-25 |
| 10091080 | Injecting lost packets and protocol errors in a simulation environment | Dirk Allmendinger, Roopesh A. Matayambath, Juergen Ruf | 2018-10-02 |
| 9934343 | System and method for generation of an integrated circuit design | Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann | 2018-04-03 |
| 9928321 | System and method for generation of an integrated circuit design | Gerrit Koch, Johannes C. Reichart, Ralf Winkelmann | 2018-03-27 |
| 9288161 | Verifying the functionality of an integrated circuit | Matayambath Roopesh Ambalath, Senthil K. Jayaraj, Juergen Ruf | 2016-03-15 |
| 9069574 | Code analysis for simulation efficiency improvement | Joerg Kayser, Roopesh A. Matayambath, Juergen Ruf | 2015-06-30 |
| 9026968 | Verification assistance for digital circuit designs | Gerrit Koch, Juergen Ruf, Ken Werner | 2015-05-05 |
| 9015685 | Code analysis for simulation efficiency improvement | Joerg Kayser, Roopesh A. Matayambath, Juergen Ruf | 2015-04-21 |