Issued Patents All Time
Showing 26–49 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9886369 | Dynamic data fabrication for database applications | Ronen Levy, Tamer Salman | 2018-02-06 |
| 9875175 | Unit-level formal verification for vehicular software systems | Fady Copty, Dmitry Pidan, Tamer Salman | 2018-01-23 |
| 9870313 | Unit-level formal verification for vehicular software systems | Fady Copty, Dmitry Pidan, Tamer Salman | 2018-01-16 |
| 9588877 | Unit-level formal verification for vehicular software systems | Fady Copty, Dmitry Pidan, Tamer Salman | 2017-03-07 |
| 9501654 | Sensitive data obfuscation in output files | Ehud Aharoni, Lev Greenberg, Roza Miroshnikov, Asaf Polakovski | 2016-11-22 |
| 8892386 | Method and apparatus for post-silicon testing | Eyal Bin, Shady Copty, Anatoly Koyfman, Shimon Landa, Amir Nahir +2 more | 2014-11-18 |
| 8806270 | Method, apparatus and product for testing transactions | Dimtry Krestyashyn, Charles Leverett Meissner, Amir Nahir | 2014-08-12 |
| 8589734 | Verifying correctness of processor transactions | John Martin Ludden, Avi Ziv | 2013-11-19 |
| 8516229 | Two pass test case generation using self-modifying instruction replacement | Brad L. Herold, John Martin Ludden, Pedro Martin-de-Nicolas, Charles Leverett Meissner, Gil Eliezer Shurek | 2013-08-20 |
| 8458652 | Device, system and method of modeling homogeneous information | Roy Emek, Eitan Marcus, Gil Eliezer Shurek | 2013-06-04 |
| 8412507 | Testing the compliance of a design with the synchronization requirements of a memory model | Sigal Asaf | 2013-04-02 |
| 8359456 | Generating random addresses for verification of distributed computerized devices | Gil Eliezer Shurek | 2013-01-22 |
| 8352525 | Generating a number based on a bitset constraint | Ehud Aharoni, Oded Margalit | 2013-01-08 |
| 8280713 | Automatic generation of test suite for processor architecture compliance | Sigal Asaf, Laurent Fournier, Itai Jaeger | 2012-10-02 |
| 8224614 | Generating a combination exerciser for executing tests on a circuit | Maxim Golubev, Andrey Klinger, Amir Nahir | 2012-07-17 |
| 8055492 | Non-unique results in design verification by test programs | — | 2011-11-08 |
| 7945888 | Model-based hardware exerciser, device, system and method thereof | Gil Eliezer Shurek | 2011-05-17 |
| 7834783 | Converting a mask constraint into a bitset constraint | Ehud Aharoni, Oded Margalit | 2010-11-16 |
| 7571201 | Method for distributed joint pseudo random decision making | Gil Eliezer Shurek | 2009-08-04 |
| 7434101 | Highly specialized scenarios in random test generation | Roy Emek, Itai Jaeger, Eitan Marcus, Tzach Schechner | 2008-10-07 |
| 7386521 | Automatic test program generation using extended conditional constraint satisfaction | Eyal Bin, Roy Emek, Kirill Shoikhet | 2008-06-10 |
| 7370296 | Modeling language and method for address translation design mechanisms in test generation | Anatoly Koyfman, Roy Emek, Yoav Katz, Michael Vinov | 2008-05-06 |
| 7133816 | Test quality through resource reallocation | Eitan Marcus, Michal Rimon, Amir Voskoboynik | 2006-11-07 |
| 6925405 | Adaptive test program generation | Roy Emek, Eitan Marcus | 2005-08-02 |