VP

Valeri Popescu

HA Hyundai Electronics America: 8 patents #6 of 148Top 5%
📍 San Diego, CA: #3,910 of 23,606 inventorsTop 20%
🗺 California: #55,401 of 386,348 inventorsTop 15%
Overall (All Time): #464,446 of 4,157,543Top 15%
11
Patents All Time

Issued Patents All Time

Showing 1–11 of 11 patents

Patent #TitleCo-InventorsDate
8782653 Fine grain performance resource management of computer systems Gary A. Gibson 2014-07-15
8677071 Control of processor cache memory occupancy Gary A. Gibson 2014-03-18
5987588 Processor architecture providing for speculative execution of instructions with multiple predictive branching and handling of trap conditions Merle A. Schultz, Gary A. Gibson, John E. Spracklen, Bruce D. Lightner 1999-11-16
5832293 Processor architecture providing speculative, out of order execution of instructions and trap handling Merle A. Schultz, Gary A. Gibson, John E. Spracklen, Bruce D. Lightner 1998-11-03
5797025 Processor architecture supporting speculative, out of order execution of instructions including multiple speculative branching Merle A. Schultz, Gary A. Gibson, John E. Spracklen, Bruce D. Lightner 1998-08-18
5708841 Processor architecture providing speculative, out of order execution of instructions Merle A. Schultz, Gary A. Gibson, John E. Spracklen, Bruce D. Lightner 1998-01-13
5627983 Processor architecture providing out-of-order execution Merle A. Schultz, Gary A. Gibson, John E. Spracklen, Bruce D. Lightner 1997-05-06
5625837 Processor architecture having out-of-order execution, speculative branching, and giving priority to instructions which affect a condition code Merle A. Schultz, Gary A. Gibson, John E. Spracklen, Bruce D. Lightner 1997-04-29
5592636 Processor architecture supporting multiple speculative branches and trap handling Merle A. Schultz, Gary A. Gibson, John E. Spracklen, Bruce D. Lightner 1997-01-07
5561776 Processor architecture supporting multiple speculative branching Merle A. Schultz, Gary A. Gibson, John E. Spracklen, Bruce D. Lightner 1996-10-01
5487156 Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched Merle A. Schultz, Gary A. Gibson, John E. Spracklen, Bruce D. Lightner 1996-01-23