Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8782653 | Fine grain performance resource management of computer systems | Valeri Popescu | 2014-07-15 |
| 8677071 | Control of processor cache memory occupancy | Valeri Popescu | 2014-03-18 |
| 8397236 | Credit based performance managment of computer systems | — | 2013-03-12 |
| 5987588 | Processor architecture providing for speculative execution of instructions with multiple predictive branching and handling of trap conditions | Valeri Popescu, Merle A. Schultz, John E. Spracklen, Bruce D. Lightner | 1999-11-16 |
| 5832293 | Processor architecture providing speculative, out of order execution of instructions and trap handling | Valeri Popescu, Merle A. Schultz, John E. Spracklen, Bruce D. Lightner | 1998-11-03 |
| 5797025 | Processor architecture supporting speculative, out of order execution of instructions including multiple speculative branching | Valeri Popescu, Merle A. Schultz, John E. Spracklen, Bruce D. Lightner | 1998-08-18 |
| 5708841 | Processor architecture providing speculative, out of order execution of instructions | Valeri Popescu, Merle A. Schultz, John E. Spracklen, Bruce D. Lightner | 1998-01-13 |
| 5627983 | Processor architecture providing out-of-order execution | Valeri Popescu, Merle A. Schultz, John E. Spracklen, Bruce D. Lightner | 1997-05-06 |
| 5625837 | Processor architecture having out-of-order execution, speculative branching, and giving priority to instructions which affect a condition code | Valeri Popescu, Merle A. Schultz, John E. Spracklen, Bruce D. Lightner | 1997-04-29 |
| 5592636 | Processor architecture supporting multiple speculative branches and trap handling | Valeri Popescu, Merle A. Schultz, John E. Spracklen, Bruce D. Lightner | 1997-01-07 |
| 5561776 | Processor architecture supporting multiple speculative branching | Valeri Popescu, Merle A. Schultz, John E. Spracklen, Bruce D. Lightner | 1996-10-01 |
| 5487156 | Processor architecture having independently fetching issuing and updating operations of instructions which are sequentially assigned and stored in order fetched | Valeri Popescu, Merle A. Schultz, John E. Spracklen, Bruce D. Lightner | 1996-01-23 |