Issued Patents All Time
Showing 226–250 of 259 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9189329 | Generating error correcting code (ECC) data using an ECC corresponding to an identified ECC protection level | Joseph Jun Cao, Sheng Lu, Pantas Sutardja | 2015-11-17 |
| 9189161 | Systems and methods for performing a scatter-gather data transfer operation | Zhihua Chen, Yan ZHU | 2015-11-17 |
| 9183078 | Providing error checking and correcting (ECC) capability for memory | Joseph Jun Cao | 2015-11-10 |
| 9146690 | Systems and methods for dynamic priority control | Joseph Jun Cao, Tsung-Ju Yang, Ruoyang Lu | 2015-09-29 |
| 8996844 | Apparatus and method for accessing non-overlapping portions of memory according to respective orders of dimensions | Joseph Jun Cao, Samitinjoy Pal, Hongyan Liu, Can Ma | 2015-03-31 |
| 8979003 | Filtration irrigation device | — | 2015-03-17 |
| 8959417 | Providing low-latency error correcting code capability for memory | Joseph Jun Cao, Sheng Lu, Pantas Sutardja | 2015-02-17 |
| 8949474 | Method for inter-chip and intra-chip addressing using port identifiers and address mapping | Ian A. Swarbrick, Joseph Jun Cao | 2015-02-03 |
| 8935596 | System and methods for storing data encoded with error information in a storage medium | Peter T. Liu, Joseph Jun Cao | 2015-01-13 |
| 8918348 | Web-scale entity relationship extraction | Zaiqing Nie, Xiaojiang Liu, Ji-Rong Wen | 2014-12-23 |
| 8907716 | Systems and methods for control of power semiconductor devices | Robert Gregory Wagoner, Huibin Zhu, Chengjun Wang | 2014-12-09 |
| 8826047 | Self governing power management architecture that allows independent management of devices based on clock signals and a plurality of control signals written to control registers | Ian A. Swarbrick, Joseph Jun Cao, Sheng Lu, Pantas Sutardja | 2014-09-02 |
| 8761206 | Universal packer | Zhihua Chen, Yan ZHU | 2014-06-24 |
| 8727939 | Hybrid electric drive unit, hybrid drive system and control method thereof | Hong Chen, Zhixin CHEN, Weimin Gao, Sidong Luo, Hailong Ge +2 more | 2014-05-20 |
| 8717089 | Adaptive voltage scaling using a delay line | Joseph Jun Cao, Ian A. Swarbrick | 2014-05-06 |
| 8718382 | Scalable pattern matching between a pattern clip and a pattern library | Weiping Fang, Paul C. Liu, Yuli XUE, Ke Fan | 2014-05-06 |
| 8701808 | Series/parallel dual motor multi-clutch hybrid driving unit for vehicle | Weimin Gao, Jiangang Lu, Hailong Ge, Sidong Luo, Jian Wang | 2014-04-22 |
| 8621181 | System and method for accessing distinct regions of memory using multiple mapping modes, each of the mapping modes having a predetermined order of dimensions for a respective region of the memory | Joseph Jun Cao, Samitinjoy Pal, Hongyan Liu, Can Ma | 2013-12-31 |
| 8519781 | Adaptive voltage scaling using a delay line | Joseph Jun Cao, Ian A. Swarbrick | 2013-08-27 |
| 8504490 | Web-scale entity relationship extraction that extracts pattern(s) based on an extracted tuple | Zaiqing Nie, Xiaojiang Liu, Ji-Rong Wen | 2013-08-06 |
| 8467358 | Mobile agent, radio access network, and network adaptation method | Lijing Miao, Jian Wu, Zongfang Cui, Yongzhi Chen | 2013-06-18 |
| 8448001 | System having a first device and second device in which the main power management module is configured to selectively supply a power and clock signal to change the power state of each device independently of the other device | Ian A. Swarbrick, Joseph Jun Cao, Sheng Lu, Pantas Sutardja | 2013-05-21 |
| 8402249 | System and method for mixed-mode SDRAM address mapping | Joseph Jun Cao, Samitinjoy Pal, Hongyan Liu, Can Ma | 2013-03-19 |
| 8378738 | Adaptive voltage scaling using a delay line | Joseph Jun Cao, Ian A. Swarbrick | 2013-02-19 |
| 8352837 | System and methods for storing data encoded with error information in a storage medium | Peter T. Liu, Joseph Jun Cao | 2013-01-08 |