Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10198310 | Providing error correcting code (ECC) capability for memory | Jun Zhu, Sheng Lu, Pantas Sutardja | 2019-02-05 |
| 9958884 | Universal adaptive voltage scaling system | Jun Zhu, Liping Guo | 2018-05-01 |
| 9524255 | System and method for automatic DQS gating based on counter signal | Jun Zhu, Shawn Chen | 2016-12-20 |
| 9507742 | Variable length arbitration | Jun Zhu, Sheng Lu | 2016-11-29 |
| 9411753 | Systems and methods for dynamically determining a priority for a queue of commands | Jun Zhu, Tsung-Ju Yang, Ruoyang Lu | 2016-08-09 |
| 9396146 | Timing-budget-based quality-of-service control for a system-on-chip | Pantas Sutardja, Jun Zhu | 2016-07-19 |
| 9367347 | Systems and methods for command execution order control in electronic systems | Jun Zhu, Tsung-Ju Yang, Ruoyang Lu | 2016-06-14 |
| 9285824 | Systems and methods for DQS gating | Jun Zhu, Sheng Lu | 2016-03-15 |
| 9264368 | Chip-to-chip communications | Ian A. Swarbrick | 2016-02-16 |
| 9264030 | Adaptive voltage scaling using a delay line | Jun Zhu, Ian A. Swarbrick | 2016-02-16 |
| 9223327 | Universal adaptive voltage scaling system | Jun Zhu, Liping Guo | 2015-12-29 |
| 9189329 | Generating error correcting code (ECC) data using an ECC corresponding to an identified ECC protection level | Jun Zhu, Sheng Lu, Pantas Sutardja | 2015-11-17 |
| 9183078 | Providing error checking and correcting (ECC) capability for memory | Jun Zhu | 2015-11-10 |
| 9146690 | Systems and methods for dynamic priority control | Jun Zhu, Tsung-Ju Yang, Ruoyang Lu | 2015-09-29 |
| 9116836 | Tunneling transaction packets | David Geddes, Scott Furey | 2015-08-25 |
| 8996844 | Apparatus and method for accessing non-overlapping portions of memory according to respective orders of dimensions | Jun Zhu, Samitinjoy Pal, Hongyan Liu, Can Ma | 2015-03-31 |
| 8959417 | Providing low-latency error correcting code capability for memory | Jun Zhu, Sheng Lu, Pantas Sutardja | 2015-02-17 |
| 8949474 | Method for inter-chip and intra-chip addressing using port identifiers and address mapping | Ian A. Swarbrick, Jun Zhu | 2015-02-03 |
| 8935596 | System and methods for storing data encoded with error information in a storage medium | Jun Zhu, Peter T. Liu | 2015-01-13 |
| 8826047 | Self governing power management architecture that allows independent management of devices based on clock signals and a plurality of control signals written to control registers | Jun Zhu, Ian A. Swarbrick, Sheng Lu, Pantas Sutardja | 2014-09-02 |
| 8717089 | Adaptive voltage scaling using a delay line | Jun Zhu, Ian A. Swarbrick | 2014-05-06 |
| 8621181 | System and method for accessing distinct regions of memory using multiple mapping modes, each of the mapping modes having a predetermined order of dimensions for a respective region of the memory | Jun Zhu, Samitinjoy Pal, Hongyan Liu, Can Ma | 2013-12-31 |
| 8519781 | Adaptive voltage scaling using a delay line | Jun Zhu, Ian A. Swarbrick | 2013-08-27 |
| 8448001 | System having a first device and second device in which the main power management module is configured to selectively supply a power and clock signal to change the power state of each device independently of the other device | Jun Zhu, Ian A. Swarbrick, Sheng Lu, Pantas Sutardja | 2013-05-21 |
| 8402249 | System and method for mixed-mode SDRAM address mapping | Jun Zhu, Samitinjoy Pal, Hongyan Liu, Can Ma | 2013-03-19 |