Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10379931 | Computer system | Hirotaka Motai, Koji Adachi, Hitoshi Suzuki | 2019-08-13 |
| 9612909 | Computer system | Hirotaka Motai, Koji Adachi, Hitoshi Suzuki | 2017-04-04 |
| 9176756 | Computer system | Hirotaka Motai, Koji Adachi, Hitoshi Suzuki | 2015-11-03 |
| 9009513 | Multiprocessor for providing timers associated with each of processor cores to determine the necessity to change operating frequency and voltage for per core upon the expiration of corresponding timer | Hitoshi Yamamoto, Akio IDEHARA | 2015-04-14 |
| 7263565 | Bus system and integrated circuit having an address monitor unit | Junichi Nishimoto | 2007-08-28 |
| 6996700 | Microcomputer and dividing circuit | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2006-02-07 |
| 6343357 | Microcomputer and dividing circuit | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2002-01-29 |
| 6272620 | Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2001-08-07 |
| 6253308 | Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2001-06-26 |
| 6205535 | Branch instruction having different field lengths for unconditional and conditional displacements | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2001-03-20 |
| 6131154 | Microcomputer having variable bit width area for displacement | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2000-10-10 |
| 6122724 | Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 2000-09-19 |
| 5991545 | Microcomputer having variable bit width area for displacement and circuit for handling immediate data larger than instruction word | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 1999-11-23 |
| 5969976 | Division circuit and the division method thereof | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 1999-10-19 |
| 5682545 | Microcomputer having 16 bit fixed length instruction format | Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao +15 more | 1997-10-28 |