Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11972589 | Image processing device, work robot, substrate inspection device, and specimen inspection device | Masafumi Amano, Nobuo OISHI, Takato Namekata | 2024-04-30 |
| 5481484 | Mixed mode simulation method and simulator | Munehiro Ogawa, deceased, Hitoshi Sugihara, Saburo Hojo, Masami Kinoshita, Osamu Yamashiro +2 more | 1996-01-02 |
| 5477067 | Semiconductor IC device having a RAM interposed between different logic sections and by-pass signal lines extending over the RAM for mutually connecting the logic sections | Satoru Isomura, Katsumi Ogiue | 1995-12-19 |
| 5399912 | Hold-type latch circuit with increased margin in the feedback timing and a memory device using same for holding parity check error | Shigeharu Murata, Takasi Oomori, Masami Usami | 1995-03-21 |
| 5388073 | Semiconductor integrated circuit device and digital processor employing the same | Masami Usami, Akihisa Uchida, Yoshino Sakai | 1995-02-07 |
| 5243208 | Semiconductor integrated circuit device having a gate array with a ram and by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array | Satoru Isomura, Katsumi Ogiue | 1993-09-07 |
| 5103282 | Semiconductor integrated circuit device having a gate array with a RAM and by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array | Satoru Isomura, Katsumi Ogiue | 1992-04-07 |
| 4970687 | Semiconductor memory device having a timing generator circuit which provides a write pulse signal which has an optional timing relationship with the chip select signal | Masami Usami, Kazuhiro Akimoto, Takeo Uchiyama | 1990-11-13 |
| 4959704 | Semiconductor integrated circuit device | Satoru Isomura, Katsumi Ogiue | 1990-09-25 |
| 4219369 | Method of making semiconductor integrated circuit device | Katsumi Ogiue, Takahisa Nitta, Kazumichi Mitsusada, Masanori Odaka | 1980-08-26 |