Issued Patents All Time
Showing 26–50 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5677880 | Semiconductor memory having redundancy circuit | Masashi Horiguchi, Masakazu Aoki, Yoshinobu Nakagome, Hitoshi Tanaka, Kiyoo Itoh | 1997-10-14 |
| 5617365 | Semiconductor device having redundancy circuit | Masashi Horiguchi, Masakazu Aoki, Kiyoo Itoh | 1997-04-01 |
| 5602771 | Semiconductor memory device and defect remedying method thereof | Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki +17 more | 1997-02-11 |
| 5579256 | Semiconductor memory device and defect remedying method thereof | Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki +17 more | 1996-11-26 |
| 5539279 | Ferroelectric memory | Kan Takeuchi, Masashi Horiguchi, Masakazu Aoki, Katsumi Matsuno, Takeshi Sakata +1 more | 1996-07-23 |
| 5526313 | Large scale integrated circuit with sense amplifier circuits for low voltage operation | Kiyoo Itoh, Yoshiki Kawajiri, Yoshinobu Nakagome, Eiji Kume, Hitoshi Tanaka | 1996-06-11 |
| 5467314 | Method of testing an address multiplexed dynamic RAM | Kazuyuki Miyazawa, Katsuhiro Shimohigashi, Katsutaka Kimura | 1995-11-14 |
| 5455797 | Reference voltage generator | Yoshinobu Nakagome, Hitoshi Tanaka, Koji Kawamoto, Masakazu Aoki | 1995-10-03 |
| 5426616 | Semiconductor IC device having a voltage conversion circuit which generates an internal supply voltage having value compensated for external supply voltage variations | Kazuhiko Kajigaya, Tetsu Udagawa, Kyoko Ishii, Manabu Tsunozaki, Kazuyoshi Oshima +4 more | 1995-06-20 |
| 5402376 | Semiconductor memory having redundancy circuit | Masashi Horiguchi, Masakazu Aoki, Yoshinobu Nakagome, Hitoshi Tanaka, Kiyoo Itoh | 1995-03-28 |
| 5384740 | Reference voltage generator | Yoshinobu Nakagome, Hitoshi Tanaka, Koji Kawamoto, Masakazu Aoki | 1995-01-24 |
| 5383080 | Semiconductor integrated circuit having voltage limiter circuit | Masakazu Aoki, Masashi Horiguchi, Shigeki Ueda, Hitoshi Tanaka, Kazuhiko Kajigaya +2 more | 1995-01-17 |
| 5376839 | Large scale integrated circuit having low internal operating voltage | Masashi Horiguchi, Masakazu Aoki, Kiyoo Itoh, Yoshinobu Nakagome, Norio Miyake +3 more | 1994-12-27 |
| 5331596 | Address multiplexed dynamic RAM having a test mode capability | Kazuyuki Miyazawa, Katsuhiro Shimohigashi, Katsutaka Kimura | 1994-07-19 |
| 5297097 | Large scale integrated circuit for low voltage operation | Kiyoo Itoh, Yoshiki Kawajiri, Yoshinobu Nakagome, Eiji Kume, Hitoshi Tanaka | 1994-03-22 |
| 5265055 | Semiconductor memory having redundancy circuit | Masashi Horiguchi, Masakazu Aoki, Kiyoo Itoh | 1993-11-23 |
| 5262993 | Semiconductor memory having redundancy circuit with means to switch power from a normal memory block to a spare memory block | Masashi Horiguchi, Masakazu Aoki, Yoshinobu Nakagome, Hitoshi Tanaka, Kiyoo Itoh | 1993-11-16 |
| 5262999 | Large scale integrated circuit for low voltage operation | Kiyoo Itoh, Yoshiki Kawajiri, Yoshinobu Nakagome, Eiji Kume, Hitoshi Tanaka | 1993-11-16 |
| 5254880 | Large scale integrated circuit having low internal operating voltage | Masashi Horiguchi, Masakazu Aoki, Kiyoo Itoh, Yoshinobu Nakagome, Norio Miyake +3 more | 1993-10-19 |
| 5179539 | Large scale integrated circuit having low internal operating voltage | Masashi Horiguchi, Masakazu Aoki, Kiyoo Itoh, Yoshinobu Nakagome, Norio Miyake +3 more | 1993-01-12 |
| 5117393 | Method of testing memory cells in an address multiplexed dynamic RAM including test mode selection | Kazuyuki Miyazawa, Katsuhiro Shimohigashi, Katsutaka Kimura | 1992-05-26 |
| 5086414 | Semiconductor device having latch means | Hiroaki Nambu, Noriyuki Homma, Kunihiko Yamaguchi, Kazuo Kanetani, Youji Idei +2 more | 1992-02-04 |
| 4994688 | Semiconductor device having a reference voltage generating circuit | Masashi Horiguchi, Masakazu Aoki, Kiyoo Itoh, Yoshinobu Nakagome, Norio Miyake +3 more | 1991-02-19 |
| 4992985 | Method for selectively initiating/terminating a test mode in an address multiplexed DRAM and address multiplexed DRAM having such a capability | Kazuyuki Miyazawa, Katsuhiro Shimohigashi, Katsutaka Kimura | 1991-02-12 |
| 4965769 | Semiconductor memory capable of high-speed data erasing | Kiyoo Itoh, Masakazu Aoki, Ryoichi Hori | 1990-10-23 |