Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9405873 | Method for improved accuracy of a substrate parasitic-resistance extraction in a circuit simulation | Toshiki Kanamoto | 2016-08-02 |
| 6578184 | Circuit design method and circuit design apparatus | Masanori Fukuda, Hiroaki Sugimoto | 2003-06-10 |